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73S1210F の電気的特性と機能

73S1210FのメーカーはTeridian Semiconductorです、この部品の機能は「Self-Contained Smart Card Reader」です。


製品の詳細 ( Datasheet PDF )

部品番号 73S1210F
部品説明 Self-Contained Smart Card Reader
メーカ Teridian Semiconductor
ロゴ Teridian Semiconductor ロゴ 




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73S1210F Datasheet, 73S1210F PDF,ピン配置, 機能
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73S1210F
Self-Contained Smart Card Reader
with PINpad and Power Management
Simplifying System Integration™
DATA SHEET
May 2009
GENERAL DESCRIPTION
The 73S1210F is a versatile and economical CMOS
System-on-Chip device intended for smart card reader
applications. The circuit is built around an 80515 high-
performance core; it features primarily an ISO-7816 / EMV
interface and a generic asynchronous serial interface.
Delivered with turnkey Teridian embedded firmware, it
forms a ready-to-use smart card reader solution that can be
seamlessly incorporated into any microprocessor-based
system where a serial line is available.
The solution is scalable, thanks to a built-in I2C interface
that allows to drive external electrical smart card interfaces
such as Teridian 73S8010 ICs. This makes the solution
immediately able to support multi-card slots or multi-SAM
architectures.
In addition, the 73S1210 features a 5x6 PINpad interface, 8
user I/Os, multiple interrupt options and an analog voltage
input (for DC voltage monitoring such as battery level
detection) that make it suitable for low-cost PINpad reader
devices.
The 80515 CPU core instruction set is compatible with the
industry standard 8051, while offering one clock-cycle per
instruction processing power (most instructions). With a
CPU clock running up to 24MHz, it results in up to 24MIPS
available that meets the requirements of various encryption
needs such as AES, DES / 3-DES and even RSA (for PIN
encryption for instance).
The circuit requires a single 6MHz to 12MHz crystal.
The respective 73S1210F embedded memories are 32KB
Flash program memory, 2KB user XRAM memory, and
256B IRAM memory. Dedicated FIFOs for the ISO 7816
UART are independent from the user XRAM and IRAM.
Alternatively to the turnkey firmware offered by Teridian,
customers can develop their own embedded firmware
directly within their application or using Teridian 73S1210F
Evaluation Board through a JTAG-like interface.
The chip incorporates an inductor-based DC-DC converter
that generates all the necessary voltages to the various
73S1210F function blocks (smart card interface, digital
core, etc.) from any of two distinct power supply sources:
the +5V bus (VBUS, 4.4 to 6.5V), or a main battery (VBAT,
4.0V to 6.5V). The chip automatically powers-up the DC-
DC converter with VBUS if it is present, or uses VBAT as the
supply input if VBUS is not present. Alternatively, the pin VPC
can support a wider power supply input range (2.7V to
6.5V), when using a single system supply source.
In addition, the circuit features an ON/OFF mode which
operates directly with an ON/OFF system switch: Any
activity on the ON/OFF button is debounced internally
and controls the power generation circuit accordingly,
under the supervision of the firmware (OFF request /
OFF acknowledgement at firmware level). The OFF
mode can be alternatively initiated from the controller
(firmware action instead of ON/OFF switch).
In OFF mode, the circuit typically draws less than 1µA,
which makes it ideal for applications where battery life
must be maximized.
Embedded Flash memory is in-system programmable
and lockable by means of on-silicon fuses. This makes
the 73S1210F suitable for both development and
production phases.
Teridian Semiconductor Corporation offers with its
73S1210F a very comprehensive set of software
libraries for EMV. Refer to the 73S12xxF Software
User’s Guide for a complete description of the
Application Programming Interface (API Libraries) and
related software modules.
A complete array of development and programming
tools, libraries and demonstration boards enable rapid
development and certification of readers that meet
most demanding smart card standards.
APPLICATIONS
PINpad smart card readers:
o With serial connectivity
o Ideal for low-cost POS Terminals and Digital
Identification (Secure Login, Gov’t ID, ...)
SIM Readers in Personal Wireless devices
Payphones & Vending machines
General purpose smart card readers
ADVANTAGES
Reduced BOM
Versatile power supply options
o 2.7V to 6.5V ranges
Higher performance CPU core (up to 24MIPS)
Built-in EMV/ISO slot, expandable to multi-slots
Flexible power supply options
o On-chip DC-DC converter
o CMOS switches between supply inputs
Sub-µA Power Down mode with ON/OFF switch
Powerful In-Circuit Emulation and Programming
A complete set of EMV4.1 / ISO7816 libraries
Turnkey PC/SC firmware and host drivers
o Multiple OS supported
Rev. 1.4
© 2009 Teridian Semiconductor Corporation
1

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73S1210F pdf, ピン配列
DS_1210F_001
73S1210wFwDwa.DtaataSShheeete4Ut .com
Table of Contents
1 Hardware Description......................................................................................................................... 8
1.1 Pin Description............................................................................................................................. 8
1.2 Hardware Overview ................................................................................................................... 11
1.3 80515 MPU Core ....................................................................................................................... 11
1.3.1 80515 Overview............................................................................................................. 11
1.3.2 Memory Organization .................................................................................................... 11
1.4 Program Security ....................................................................................................................... 16
1.5 Special Function Registers (SFRs) ........................................................................................... 18
1.5.1 Internal Data Special Function Registers (SFRs).......................................................... 18
1.5.2 IRAM Special Function Registers (Generic 80515 SFRs) ............................................ 19
1.5.3 External Data Special Function Registers (SFRs) ........................................................ 20
1.6 Instruction Set ............................................................................................................................ 22
1.7 Peripheral Descriptions.............................................................................................................. 22
1.7.1 Oscillator and Clock Generation.................................................................................... 22
1.7.2 Power Supply Management .......................................................................................... 25
1.7.3 Power ON/OFF .............................................................................................................. 26
1.7.4 Power Control Modes .................................................................................................... 27
1.7.5 Interrupts........................................................................................................................ 33
1.7.6 UART ............................................................................................................................. 40
1.7.7 Timers and Counters ..................................................................................................... 45
1.7.8 WD Timer (Software Watchdog Timer) ......................................................................... 47
1.7.9 User (USR) Ports........................................................................................................... 49
1.7.10 Analog Voltage Comparator .......................................................................................... 51
1.7.11 LED Driver ..................................................................................................................... 53
1.7.12 I2C Master Interface ....................................................................................................... 54
1.7.13 Keypad Interface............................................................................................................ 61
1.7.14 Emulator Port ................................................................................................................. 68
1.7.15 Smart Card Interface Function ...................................................................................... 69
1.7.16 VDD Fault Detect Function .......................................................................................... 103
2 Typical Application Schematic ...................................................................................................... 104
3 Electrical Specification................................................................................................................... 105
3.1 Absolute Maximum Ratings ..................................................................................................... 105
3.2 Recommended Operating Conditions ..................................................................................... 105
3.3 Digital IO Characteristics ......................................................................................................... 106
3.4 Oscillator Interface Requirements ........................................................................................... 107
3.5 DC Characteristics: Analog Input............................................................................................. 107
3.6 Smart Card Interface Requirements ........................................................................................ 108
3.7 DC Characteristics ................................................................................................................... 110
3.8 Current Fault Detection Circuits............................................................................................... 111
4 Equivalent Circuits ......................................................................................................................... 112
5 Package Pin Designation ............................................................................................................... 120
5.1 68-pin QFN Pinout ................................................................................................................... 120
5.2 44-pin QFN Pinout ................................................................................................................... 121
6 Packaging Information ................................................................................................................... 122
6.1 68-Pin QFN Package Outline .................................................................................................. 122
6.2 44-Pin QFN Package Outline .................................................................................................. 123
7 Ordering Information ...................................................................................................................... 124
8 Related Documentation.................................................................................................................. 124
9 Contact Information........................................................................................................................ 124
Revision History...................................................................................................................................... 125
Rev. 1.4
3


3Pages


73S1210F 電子部品, 半導体
73S1210F Data Sheet
DSw_w1w2.D1a0taFS_he0e0t41U.com
Table 57: The DAR Register....................................................................................................................... 57
Table 58: The WDR Register...................................................................................................................... 57
Table 59: The SWDR Register ................................................................................................................... 58
Table 60: The RDR Register....................................................................................................................... 58
Table 61: The SRDR Register .................................................................................................................... 59
Table 62: The CSR Register....................................................................................................................... 59
Table 63: The INT6Ctl Register .................................................................................................................. 60
Table 64: The KCOL Register..................................................................................................................... 64
Table 65: The KROW Register ................................................................................................................... 64
Table 66: The KSCAN Register .................................................................................................................. 65
Table 67: The KSTAT Register................................................................................................................... 65
Table 68: The KSIZE Register .................................................................................................................... 66
Table 69: The KORDERL Register ............................................................................................................. 67
Table 70: The KORDERH Register ............................................................................................................ 67
Table 71: The INT5Ctl Register .................................................................................................................. 68
Table 72: The SCSel Register .................................................................................................................... 80
Table 73: The SCInt Register ..................................................................................................................... 81
Table 74: The SCIE Register ...................................................................................................................... 82
Table 75: The VccCtl Register .................................................................................................................... 83
Table 76: The VccTmr Register .................................................................................................................. 84
Table 77: The CRDCtl Register .................................................................................................................. 85
Table 78: The STXCtl Register ................................................................................................................... 86
Table 79: The STXData Register................................................................................................................ 87
Table 80: The SRXCtl Register................................................................................................................... 87
Table 81: The SRXData Register ............................................................................................................... 88
Table 82: The SCCtl Register ..................................................................................................................... 89
Table 83: The SCECtl Register................................................................................................................... 90
Table 84: The SCDIR Register ................................................................................................................... 91
Table 85: The SPrtcol Register................................................................................................................... 92
Table 86: The SCCLK Register .................................................................................................................. 93
Table 87: The SCECLK Register ................................................................................................................ 93
Table 88: The SParCtl Register .................................................................................................................. 94
Table 89: The SByteCtl Register ................................................................................................................ 95
Table 90: The FDReg Register ................................................................................................................... 96
Table 91: The FDReg Bit Functions............................................................................................................ 96
Table 92: Divider Ratios Provided by the ETU Counter ............................................................................. 96
Table 93: Divider Values for the ETU Clock ............................................................................................... 97
Table 94: The CRCMsB Register ............................................................................................................... 98
Table 95: The BGT Register ....................................................................................................................... 99
Table 96: The EGT Register ....................................................................................................................... 99
Table 97: The BWTB0 Register ................................................................................................................ 100
Table 98: The BWTB1 Register ................................................................................................................ 100
Table 99: The BWTB2 Register ................................................................................................................ 100
Table 100: The BWTB3 Register .............................................................................................................. 100
Table 101: The CWTB0 Register.............................................................................................................. 100
Table 102: The CWTB1 Register.............................................................................................................. 100
Table 103: The ATRLsB Register ............................................................................................................. 101
Table 104: The ATRMsB Register ............................................................................................................ 101
Table 105: The STSTO Register .............................................................................................................. 101
Table 106: The RLength Register............................................................................................................. 101
Table 107: Smart Card SFR Table ........................................................................................................... 102
Table 108: The VDDFCtl Register ............................................................................................................ 103
Table 109: Order Numbers and Packaging Marks ................................................................................... 124
6 Rev. 1.4

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部品番号部品説明メーカ
73S1210F

Self-Contained Smart Card Reader

Teridian Semiconductor
Teridian Semiconductor


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