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PDF 73S1217F Data sheet ( Hoja de datos )
| Número de pieza | 73S1217F | |
| Descripción | Bus-Powered 80515 System-on-Chip | |
| Fabricantes | Teridian Semiconductor | |
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73S1217Fwww.DataSheet4U.com
Bus-Powered 80515 System-on-Chip with USB,
ISO 7816 / EMV, PINpad and More
Simplifying System Integration™
DATA SHEET
December 2008
GENERAL DESCRIPTION
The Teridian Semiconductor Corporation 73S1217F is a
versatile and economical CMOS System-on-Chip device
intended for smart card reader applications. The circuit
features an ISO-7816 / EMV interface, an USB 2.0
interface (full-speed 12Mbps - slave) and a 5x6 PINpad
interface. Additional features include 8 user I/Os,
multiple interrupt options and an analog voltage input (for
DC voltage monitoring such as battery level detection).
Other built-in interfaces include an asynchronous serial
and an I2C interface.
The System-on-Chip is built around an 80515 high-
performance core. Its feature and instruction set is
compatible with the industry standard 8051, while
offering one clock-cycle per instruction processing
power (most instructions). With a CPU clock running up
to 24MHz, it results in up to 20MIPS available that
meets the requirements of various encryption needs
such as AES, DES / 3-DES and even RSA (for PIN
encryption for instance). The circuit requires a single 6
to 12 MHz crystal. An optional 32kHz crystal can be
connected to a sub-system oscillator with a real-time-
clock counter to enable stand-alone applications to
access an RTC value.
The respective 73S1217F embedded memories are;
64KB Flash program memory, 2KB user XRAM
memory, and 256B IRAM memory. On top of these
memories are added independent FIFOs dedicated to
the ISO7816 UART and to the USB interface.
The chip incorporates an inductor-based DC-DC
converter that generates all the necessary voltages to
the various 73S1217F function blocks (smart card
interface, digital core, etc.) from any of two distinct
power supply sources: The +5V USB bus (VBUS, 4.4V to
6.5V), or a main battery (VBAT, 4.0V to 6.5V). The chip
automatically powers-up the DC-DC converter with VBUS
if it is present, or uses VBAT as the supply input.
Alternatively, the pin VPC can support a wider power
supply input range (2.7V to 6.5V), when using a single
system supply source.
In addition, the circuit features an ON/OFF mode which
operates directly with an ON/OFF system switch: Any
activity on the ON/OFF button is debounced internally
and controls the power generation circuit accordingly,
under the supervision of the firmware (OFF request /
OFF acknowledgement at firmware level). The OFF
mode can be alternatively initiated from the controller
(firmware action instead of ON/OFF switch).
In OFF mode, the circuit typically draws less than 1μA,
which makes it ideal for applications where battery life
must be maximized.
Wake-up of the controller upon USB cable insertion is
supported.
Embedded Flash memory is in-system programmable
and lockable by means of on-silicon fuses. This makes
the Teridian 73S1217F suitable for both development and
production phases.
Teridian Semiconductor Corporation offers with its
73S1217F a very comprehensive set of software libraries,
including the smart card and USB protocol layers that are
pre-approved against USB, Microsoft WHQL and EMV,
as well as a CCID reference design. Refer to the
Teridian Semiconductor Corporation 73S12xxF Software
User’s Guide for a complete description of the Application
Programming Interface (API Libraries) and related
Software modules.
A complete array of development and programming
tools, libraries and demonstration boards enable
rapid development and certification of readers that
meet most demanding smart card standards.
APPLICATIONS
• Hand-held PINpad smart card readers:
• With USB or serial connectivity
• Ideal for E-banking (MasterCard CAP, etc) and Digital
Identification (Secure Login, Gov’t ID...)
• Transparent USB card readers and USB keys
• General purpose smart card readers
ADVANTAGES
• Reduced BOM
• Larger built-in Flash / RAM than its competitors
• Higher performance CPU core (up to 24MIPS)
• On-chip DC-DC converter and CMOS switches for
battery and USB power
• Sub-μA Power Down mode with ON/OFF switch
• Powerful In-Circuit Emulation and Programming
• A complete set of EMV4.1, USB and CCID libraries
• Overall, the ideal compromise cost / features for high
volume, PINpad reader applications!
Rev. 1.2
© 2008 Teridian Semiconductor Corporation
1
1 page  
DS_1217F_002
73S1217wFwDwa.DtaataSShheeete4Ut .com
Tables
Table 1: 73S1217 Pinout Description ........................................................................................................... 8
Table 2: MPU Data Memory Map ............................................................................................................... 11
Table 3: Flash Special Function Registers ................................................................................................. 13
Table 4: Internal Data Memory Map ........................................................................................................... 14
Table 5: Program Security Registers .......................................................................................................... 17
Table 6: IRAM Special Function Registers Locations ................................................................................ 18
Table 7: IRAM Special Function Registers Reset Values .......................................................................... 19
Table 8: XRAM Special Function Registers Reset Values ......................................................................... 20
Table 9: PSW Register Flags...................................................................................................................... 22
Table 10: Port Registers ............................................................................................................................. 22
Table 11: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 24
Table 12: The MCLKCtl Register ................................................................................................................ 24
Table 13: The MPUCKCtl Register ............................................................................................................. 25
Table 14: The INT5Ctl Register .................................................................................................................. 31
Table 15: The MISCtl0 Register.................................................................................................................. 31
Table 16: The MISCtl1 Register.................................................................................................................. 32
Table 17: The MCLKCtl Register ................................................................................................................ 33
Table 18: The PCON Register .................................................................................................................... 34
Table 19: The IEN0 Register ...................................................................................................................... 36
Table 20: The IEN1 Register ...................................................................................................................... 37
Table 21: The IEN2 Register ...................................................................................................................... 37
Table 22: The TCON Register .................................................................................................................... 38
Table 23: The T2CON Register .................................................................................................................. 38
Table 24: The IRCON Register................................................................................................................... 39
Table 25: External MPU Interrupts.............................................................................................................. 39
Table 26: Control Bits for External Interrupts.............................................................................................. 40
Table 27: Priority Level Groups .................................................................................................................. 40
Table 28: The IP0 Register ......................................................................................................................... 40
Table 29: The IP1 Register ......................................................................................................................... 41
Table 30: Priority Levels.............................................................................................................................. 41
Table 31: Interrupt Polling Sequence.......................................................................................................... 41
Table 32: Interrupt Vectors ......................................................................................................................... 41
Table 33: UART Modes .............................................................................................................................. 42
Table 34: Baud Rate Generation ................................................................................................................ 42
Table 35: The PCON Register .................................................................................................................... 43
Table 36: The BRCON Register ................................................................................................................. 43
Table 37: The MISCtl0 Register.................................................................................................................. 44
Table 38: The S0CON Register .................................................................................................................. 45
Table 39: The S1CON Register .................................................................................................................. 46
Table 40: The TMOD Register.................................................................................................................... 47
Table 41: Timers/Counters Mode Description ............................................................................................ 48
Table 42: The TCON Register .................................................................................................................... 49
Table 43: The IEN0 Register ...................................................................................................................... 50
Table 44: The IEN1 Register ...................................................................................................................... 50
Table 45: The IP0 Register ......................................................................................................................... 51
Table 46: The WDTREL Register ............................................................................................................... 51
Table 47: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 52
Table 48: UDIR Control Bit ......................................................................................................................... 52
Table 49: Selectable Controls Using the UxIS Bits..................................................................................... 52
Table 50: The USRIntCtl1 Register ............................................................................................................ 53
Table 51: The USRIntCtl2 Register ............................................................................................................ 53
Table 52: The USRIntCtl3 Register ............................................................................................................ 53
Table 53: The USRIntCtl4 Register ............................................................................................................ 53
Table 54: The RTCCtl Register................................................................................................................... 55
Table 55: The 32-bit RTC Counter.............................................................................................................. 56
Table 56: The 24-bit RTC Accumulator ...................................................................................................... 56
Table 57: The 24-bit RTC Trim (sign magnitude value) ............................................................................. 56
Rev. 1.2
5
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DS_1217F_002
73S1217wFwDwa.DtaataSShheeete4Ut .com
1.2 Hardware Overview
The 73S1217F single smart card controller integrates all primary functional blocks required to implement
a smart card reader with host serial and / or USB interface. Included on chip are an 8051-compatible
microprocessor (MPU) which executes up to one instruction per clock cycle (80515), a fully integrated IS0
7816 compliant smart card interface, expansion smart card interface, full speed USB 2.0 compatible
interface, serial interface, I2C interface, 6 x 5 keypad interface, RAM, FLASH memory, a real time clock
(RTC), and a variety of I/O pins.
Advanced power management features include a DC-DC converter and on-chip regulators that generate
all the necessary voltages for the circuit: Primarily a smart card supply VCC, (selectable to 1.8V, 3V or
5V) and a 3.3V digital voltage output (VDD, pin #68) that must be connected to the power supply inputs of
the digital core of the circuit, pins # 28 and 40 (these are not internally connected). Should external
circuitry require a 3.3V digital power supply, the VDD output is capable of supplying additional current.
The whole IC can be powered up either from a USB bus-power supply (VBUS +5V typical), or from a
typical set of battery cells VBAT. Automated switching between these supply inputs give the priority to
VBUS to save the battery life.
A functional block diagram of the 73S1217F is shown in Figure 1.
1.3 80515 MPU Core
1.3.1 80515 Overview
The 73S1217F includes an 80515 MPU (8-bit, 8051-compatible) that performs most instructions in one
clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution
of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most
of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (average)
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application
(cryptographic calculations, key management, memory management, and I/O management) using the
XRAM special function register MPUCKCtl.
Typical smart card, USB, serial, keyboard, I2C and RTC management functions are available for the
MPU as part of the Teridian standard library. A standard ANSI “C” 80515-application programming
interface library is available to help reduce design cycle. Refer to the 73S12xxF Software User’s Guide.
1.3.2 Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three
memory areas: Program memory (Flash), external data memory (XRAM), and internal data memory
(IRAM). Data bus address space is allocated to on-chip memory as shown Table 2.
Table 2: MPU Data Memory Map
Address
(hex)
0000-FFFF
Memory
Technology
Flash Memory
Memory Type
Non-volatile
0000-07FF
FC00-FFFF
Static RAM
External SFR
Volatile
Volatile
Typical Usage
Program and non-volatile
data
MPU data XRAM
Peripheral control
Note: The IRAM is part of the core and is addressed differently.
Memory Size
(bytes)
64KB
2KB
1KB
Rev. 1.2
11
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