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PDF 78P2352 Data sheet ( Hoja de datos )
| Número de pieza | 78P2352 | |
| Descripción | Dual Channel OC-3/ STM1-E/ E4 LIU | |
| Fabricantes | TDK Semiconductor | |
| Logotipo |  |
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DESCRIPTION
The 78P2352 is TDK’s second generation LIU for
155 Mbit/s SDH/SONET (OC-3, STS-3, or STM-1)
and 140Mbit/s PDH (E4) applications. The device is
a dual channel, single chip solution that includes an
integrated CDR in the transmit path for flexible NRZ
to CMI conversion. The device can interface to 75Ω
coaxial cable using CMI coding or directly to a fiber
optics module using NRZ coding. The 78P2352 is
compliant with all respective ANSI, ITU-T, and
Telcordia standards for jitter tolerance, generation,
and transfer.
APPLICATIONS
• Central Office Interconnects
• DSLAMs
• Add Drop Multiplexers (ADMs)
• PDH/SDH test equipment
BLOCK DIAGRAM
78P2352www.DataSheet4U.com
Dual Channel
OC-3/ STM1-E/ E4 LIU
TARGET DATASHEET
MARCH 2003
FEATURES
• G.703 compliant line interface for 139.264 Mbps
or 155.52 Mbps CMI-coded coax transmission.
• LVPECL compatible line interface for 155.52
Mbps NRZ-coded fiber applications.
• Integrated adaptive CMI equalizer and CDR in
receive path.
• Serial, LVPECL-compatible system interface
with integrated CDR in transmit path for NRZ to
CMI conversion.
• 4-bit parallel CMOS system interface with
master/slave Tx clock modes.
• Configurable via HW control pins or 4-wire µP
interface
• Operates from a single reference clock input.
• Compliant with ANSI T1.105.03-1994; ITU-T
G.751, G.813, G.823, G.825, G.958; and
Telcordia GR-253-CORE for jitter performance.
• Provides Loss of Lock (LOL), CMI Line Code
Violation (LCV), and G.775 compliant Loss of
Signal (LOS) detection.
• Receiver Monitor Mode
• Operates from a single 3.3V supply
• 128-pin TQFP (JEDEC LQFP) package
SIxDP/N
SIxCKP/N
PIxCK
PIx[3:0]D
PTOxCK
SOxCKP/N
SOxDP/N
POx[3:0]D
POxCK
Lock Detect
Tx CDR
FIFO
EACH CHANNEL: Tx
CMI
Encoder
CMI
Decoder
CMI-LCV
Detect
Rx CDR
Lock Detect
EACH CHANNEL: Rx
Adaptive
Eq.
G.775
LOS
Detect
TXxCKP/N
CMIxP/N
ECLxP/N
RXxP/N
1
1 page  
78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
www.DataSheet4U.com
TRANSMITTER OPERATION
The transmitter section generates an analog signal
for transmission through either a transformer onto
the coaxial cable or directly to a fiber optics module.
Each of the described transmit serial modes can be
configured in HW mode and SW mode as shown in
the table below:
The 78P2352 provides a flexible system interface for
compatibility with most off-the-shelf framers and
custom ASICs. The device supports a 4-bit parallel
interface in either slave or master clocking modes
and a number of serial NRZ modes.
Serial Modes
In Figure 1, serial NRZ data is input to the 78P2352
on the SIDxP/N pins at LVPECL levels. The data is
latched in on the rising edge of SICKxP/N. A clock
decoupling FIFO is provided to decouple the on chip
and off chip clocks. The SICKxP/N clock provided
by the framer/mapper IC should be source
synchronous with the internal reference transmit
clock if the FIFO is to be used. Since both clocks go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The FIFO is designed to allow long-term clock phase
drift not exceeding +/- 25.6ns to be handled without
transmit error. If the clock wander exceeds the
specified limits, the FIFO will over or under flow, and
the FERRx register signal will be asserted. The
FIFO is then automatically re-centered. This signal
can be used to trigger an interrupt. This interrupt
event is cleared when an FRSTx pulse is applied,
and the FIFO is re-centered.
If no serial transmit clock is available, as in Figure 2,
the 78P2352 will recover a clock from the serial NRZ
data input and pass the data through the FIFO. In
this mode, the NRZ data should be source
synchronous with the reference clock applied at
CKREFP/N. Each transmitter also includes a Loss
of Lock indicator (TXLOL) which can be used to
trigger and interrupt. Note that the FIFO is
automatically re-centered when the TXLOL register
bit transitions from high to low.
HW Control Pins SW Control Bits
Serial Mode
SDI_PAR CKMODE PAR SMOD[1:0]
Synchronous
clock + data
(CDR bypass)
Low
Low
0 00
Synchronous
data
Low
Floating
0
10
Plesiochronous
data
(FIFO bypass)
Low
High
0 01
Reference
Clock
Framer/
Mapper
NRZ
140 / 155 MHz
NRZ
140 / 155 MHz
SIxDP/N
SIxCKP/N
SOxCKP/N
SOxDP/N
CKREFP/N
TDK
78P2352
CMIxP/N
CMI
Coax
XFMR
RXxP/N
CMI
Coax
XFMR
Figure 1: Synchronous; clock and data available
(Tx CDR bypassed, FIFO enabled)
Reference
Clock
Framer/
Mapper
CKREFP/N
NRZ
SIxDP/N
NRZ
140 / 155 MHz
SOxCKP/N
SOxDP/N
TDK
78P2352
CMIxP/N
CMI
Coax
XFMR
RXxP/N
CMI
Coax
XFMR
Figure 2: Synchronous; data only
(Tx CDR enabled, FIFO enabled)
Reference
Clock
Reference
Clock
Figure 3 represents the condition where no serial
transmit clock is available and the data is not source
synchronous to the reference clock input. In this
mode, the 78P2352 will recover a clock from the
serial plesiochronous data and bypass the FIFO.
Framer/
Mapper
CKREFP/N
NRZ
SIxDP/N
NRZ
140 / 155 MHz
SOxCKP/N
SOxDP/N
TDK
78P2352
CMIxP/N
CMI
Coax
XFMR
RXxP/N
CMI
Coax
XFMR
Figure 3: Plesiochronous; data only
(Tx CDR enabled, FIFO bypassed)
5
5 Page 
78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
REGISTER DESCRIPTION (CONTINUED)
www.DataSheet4U.com
PORT-SPECIFIC REGISTERS
For PA[3:0] = 1-2 = N only. Accessing a register with port address greater than 2 constitutes an invalid command,
and the read/write operation will be ignored.
ADDRESS N-0: MODE CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7 PDTX R/W
Transmitter Power-Down:
0 0 : Normal Operation
1 : Power-Down
6 PDRX R/W
Receiver Power-Down:
(Setting PDTX and PDRX for both channels will power down the
0 reference clock generator)
0 : Normal Operation
1 : Power-Down
5 PMODE R/W
Parallel Mode Interface Selection:
When PAR=1 (Master Control Regsiter: bit 5), PMODE selects the source
X
of the transmit parallel input clock, either taken from the framer externally
or generated internally.
0: Parallel clock is taken as an input to the transmitter
1: Parallel clock is given as an output from the transmitter
4 SMOD[1] R/W
X Serial Mode Interface Selection:
When PAR=0 (Master Control Regsiter: bit 5), SMOD[1:0] configures the
transmitter’s system interface.
SMOD[1] SMOD[0]
0 0 Synchronous clock and data are passed through a
FIFO. The CDR is bypassed.
1 0 Synchronous data is passed through the CDR and
3 SMOD[0] R/W
X
0
then through the FIFO.
1 Plesiochronous data is passed through the CDR to
recover a clock, but the FIFO is bypassed because
the data is not synchronous with the reference clock.
1 1 Loop Timing Mode Enable: The recovered receive
clock is used as the reference for the transmit section.
The transmit data is passed through the CDR, but the
FIFO is bypassed.
2 MON R/W
Receive Monitor Mode Enable:
0
0: Normal Operation
1: Adds 20dB of flat gain to the receive signal before equalization
NOTE: Monitor mode is only available in CMI mode.
1 -- R/W 0 Reserved
0 -- R/W 1 Reserved
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 78P2352.PDF ] | |
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