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PDF MTD6N20E Data sheet ( Hoja de datos )
| Número de pieza | MTD6N20E | |
| Descripción | Power MOSFET 6 Amps | |
| Fabricantes | ON Semiconductor | |
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MTD6N20E
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Preferred Device
Power MOSFET
6 Amps, 200 Volts
N−Channel DPAK
This advanced Power MOSFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain−to−source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor controls,
these devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating areas are critical and
offer additional safety margin against unexpected voltage transients.
Features
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Pb−Free Package is Available*
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6 AMPERES, 200 VOLTS
RDS(on) = 460 mW
N−Channel
D
G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
MARKING
DIAGRAMS
Drain−to−Source Voltage
VDSS 200 Vdc
4 Drain
Drain−to−Gate Voltage (RGS = 1.0 MW)
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp ≤ 10 ms)
Drain Current
− Continuous
− Continuous @ 100°C
− Single Pulse (tp ≤ 10 ms)
VDGR
VGS
VGSM
ID
ID
IDM
200
± 20
± 40
6.0
3.8
18
Vdc
Vdc
Vpk
Adc
Apk
12
3
4
DPAK
CASE 369C
STYLE 2
12 3
Gate Drain Source
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
PD
TJ, Tstg
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc,
IL = 6.0 Apk, L = 3.0 mH, RG = 25 W)
Thermal Resistance − Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Temperature for Soldering
Purposes, 1/8″ from case for 10 secs
EAS
RqJC
RqJA
RqJA
TL
50
0.4
1.75
−55 to
150
54
2.50
100
71.4
260
W
W/°C
W
°C
mJ
°C/W
°C
4
1
2
3
DPAK
CASE 369D
STYLE 2
4 Drain
123
6N20E Device Code
Gate Drain Source
Y = Year
WW = Work Week
G = Pb−Free Package
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using the 0.5 sq. in. drain pad size.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 3
1
Publication Order Number:
MTD6N20E/D
1 page  
12
10
8 Q1
QT
Q2
MTD6N20E
90 1000
VDD = 100 V
75
VGS
ID = 6 A
VGS = 10 V
TJ = 25°C
60 100
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6 45
4 30
ID = 6 A
TJ = 25°C
2 15
Q3 VDS
00
0 2 4 6 8 10 12 14
QT, TOTAL CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
tr
td(off)
10 td(on)
tf
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
6
VGS = 0 V
5 TJ = 25°C
4
3
2
1
0
0.5 0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1.0
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
http://onsemi.com
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| PDF Descargar | [ Datasheet MTD6N20E.PDF ] | |
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