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Datasheet MC74HC10A PDF ( 特性, スペック, ピン接続図 )

部品番号 MC74HC10A
部品説明 Triple 3-Input NAND Gate High-Performance Silicon-Gate CMOS
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 
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MC74HC10A Datasheet, MC74HC10A PDF,ピン配置, 機能
MC74HC10A
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Triple 3-Input NAND Gate
HighPerformance SiliconGate CMOS
The MC74HC10A is identical in pinout to the LS10. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the Requirements Defined JEDEC
Standard No. 7 A
Chip Complexity: 36 FETs or 9 Equivalent Gates
PbFree Packages are Available
LOGIC DIAGRAM
1
A1
2
B1
13
C1
12
Y1
3
A2
4
B2
5
C2
6
Y2
9
A3
10
B3
11
C3
8
Y3
PIN 14 = VCC
PIN 7 = GND
Y = ABC
PIN ASSIGNMENT
A1 1
B1 2
A2 3
B2 4
C2 5
Y2 6
GND 7
14 VCC
13 C1
12 Y1
11 C3
10 B3
9 A3
8 Y3
http://onsemi.com
14
1
14
1
MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
1
MC74HC10AN
AWLYYWWG
14
SOIC14
D SUFFIX
CASE 751A
1
HC10AG
AWLYWW
14
1
TSSOP14
DT SUFFIX
CASE 948G
14
HC
10A
ALYWG
G
1
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output
AB
Y
LL
LH
HL
HH
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
December, 2009 Rev. 1
1
Publication Order Number:
MC74HC10A/D

1 Page



MC74HC10A pdf, ピン配列
MC74HC10A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
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Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC – 55 to
V
25_C
v 85_C v 125_C Unit
VIH Minimum HighLevel Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
2.0 1.5 1.5 1.5
3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
V
VIL Maximum LowLevel Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
2.0 0.5 0.5 0.5
3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
V
VOH Minimum HighLevel Output
Voltage
Vin = VIH or VIL
|Iout| v 20 μA
2.0 1.9 1.9 1.9 V
4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
VOL Maximum LowLevel Output
Voltage
Vin = VIH or VIL
Vin = VIH
|Iout| v 20 μA
|Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
3.0
4.5
6.0
2.0
4.5
6.0
2.48
3.98
5.48
0.1
0.1
0.1
2.34
3.84
5.34
0.1
0.1
0.1
2.20
3.70
5.20
0.1
0.1
0.1
V
Vin = VIH or VIL
|Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin Maximum Input Leakage Current Vin = VCC or GND
6.0 ± 0.1 ± 1.0 ± 1.0 μA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 μA
6.0 1
10 40 μA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf= 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC – 55 to
V
25_C
v 85_C v 125_C Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 1 and 2)
2.0 95
3.0 45
4.5 19
6.0 16
120 145 ns
60 75
24 29
20 25
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0 75
3.0 30
4.5 15
6.0 13
95 110 ns
40 55
19 22
16 19
Cin Maximum Input Capacitance
— 10 10 10 pF
CPD Power Dissipation Capacitance (Per Gate)*
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC.
Typical @ 25°C, VCC = 5.0 V
25
pF
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MC74HC10A 電子部品, 半導体
MC74HC10A
PACKAGE DIMENSIONS
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14
1
T
SEATING
PLANE
A
G
SOIC14
CASE 751A03
ISSUE H
8
BP 7 PL
0.25 (0.010) M B M
7
C R X 45 _
F
D 14 PL
K
0.25 (0.010) M T B S A S
M
J
SOLDERING FOOTPRINT*
14X
0.58
7X
7.04
1
14X
1.52
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6

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