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MC74HC10A PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 MC74HC10A
部品説明 Triple 3-Input NAND Gate High-Performance Silicon-Gate CMOS
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 

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MC74HC10A Datasheet, MC74HC10A PDF,ピン配置, 機能
MC74HC10A
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Triple 3-Input NAND Gate
HighPerformance SiliconGate CMOS
The MC74HC10A is identical in pinout to the LS10. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the Requirements Defined JEDEC
Standard No. 7 A
Chip Complexity: 36 FETs or 9 Equivalent Gates
PbFree Packages are Available
LOGIC DIAGRAM
1
A1
2
B1
13
C1
12
Y1
3
A2
4
B2
5
C2
6
Y2
9
A3
10
B3
11
C3
8
Y3
PIN 14 = VCC
PIN 7 = GND
Y = ABC
PIN ASSIGNMENT
A1 1
B1 2
A2 3
B2 4
C2 5
Y2 6
GND 7
14 VCC
13 C1
12 Y1
11 C3
10 B3
9 A3
8 Y3
http://onsemi.com
14
1
14
1
MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
1
MC74HC10AN
AWLYYWWG
14
SOIC14
D SUFFIX
CASE 751A
1
HC10AG
AWLYWW
14
1
TSSOP14
DT SUFFIX
CASE 948G
14
HC
10A
ALYWG
G
1
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output
AB
Y
LL
LH
HL
HH
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
December, 2009 Rev. 1
1
Publication Order Number:
MC74HC10A/D

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MC74HC10A

Triple 3-Input NAND Gate High-Performance Silicon-Gate CMOS

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