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Datasheet MC74HC112A PDF ( 特性, スペック, ピン接続図 )

部品番号 MC74HC112A
部品説明 Dual J-K Flip-Flop
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 
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MC74HC112A Datasheet, MC74HC112A PDF,ピン配置, 機能
MC74HC112A
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Dual J-K Flip-Flop with
Set and Reset
HighPerformance SiliconGate CMOS
The MC74HC112A is identical in pinout to the LS112. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Each flipflop is negativeedge clocked and has activelow
asynchronous Set and Reset inputs.
The HC112A is identical in function to the HC76, but has a different
pinout.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Similar in Function to the LS112 Except When Set and Reset are
Low Simultaneously
Chip Complexity: 100 FETs or 25 Equivalent Gates
PbFree Packages are Available*
16
1
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
MC74HC112AN
AWLYYWWG
1
16
1
16
1
16
SOIC16
D SUFFIX
CASE 751B
HC112AG
AWLYWW
1
TSSOP16
DT SUFFIX
CASE 948F
16
HC
112A
ALYWG
G
1
16
1
SOEIAJ16
F SUFFIX
CASE 966
16
74HC112A
ALYWG
1
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = PbFree Package
G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
December, 2009 Rev. 7
1
Publication Order Number:
MC74HC112/D

1 Page



MC74HC112A pdf, ピン配列
MC74HC112A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
TSSOP Package†
Value
– 0.5 to + 7.0
– 1.5 to VCC + 1.5
– 0.5 to VCC + 0.5
± 20
± 25
± 50
750
500
450
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
– 65 to + 150
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP)
260
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*Maximum Ratings are those values beyond which damage to the device may occur.
Unit
V
V
V
mA
mA
mA
mW
_C
_C
Functional operation should be restricted to the Recommended Operating Conditions.
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This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC DC Supply Voltage (Referenced to GND)
2.0 6.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA Operating Temperature, All Package Types
– 55 + 125 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf Input Rise and Fall Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH
Parameter
Minimum HighLevel Input
Voltage
Test Conditions
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL MaximumLowLevelInput
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH MinimumHighLevelOutput
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVoltage
Vin = VIH or VIL
|Iout| v 20 μA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL MaximumLowLevelOutput
Voltage
Vin = VIH or VIL
Vin = VIH or VIL
|Iout| v 20 μA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin = VIH or VIL
|Iout| v 4.0 mA
|Iout| v 5.2 mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin Maximum Input Leakage Current Vin = VCC or GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC MaximumQuiescent Supply
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCurrent (per Package)
Vin = VCC or GND
Iout = 0 μA
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
Guaranteed Limit
– 55 to
25_C
v 85_C v 125_C
1.5 1.5 1.5
3.15 3.15 3.15
4.2 4.2 4.2
0.3 0.3 0.3
0.9 0.9 0.9
1.2 1.2 1.2
1.9 1.9 1.9
4.4 4.4 4.4
5.9 5.9 5.9
3.98 3.84 3.70
5.48 5.34 5.20
0.1 0.1 0.1
0.1 0.1 0.1
0.1 0.1 0.1
0.26 0.33 0.40
0.26 0.33 0.40
± 0.1
± 1.0
± 1.0
4 40 80
Unit
V
V
V
V
μA
μA
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MC74HC112A 電子部品, 半導体
MC74HC112A
PACKAGE DIMENSIONS
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A
16
1
H
G
9
B
8
PDIP16
N SUFFIX
CASE 64808
ISSUE T
FC
S
L
T
SEATING
PLANE
KJ
D 16 PL
0.25 (0.010) M T A M
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC
2.54 BSC
H 0.050 BSC
1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 _ 10 _ 0 _ 10 _
S 0.020 0.040 0.51 1.01
A
16
1
SOIC16
D SUFFIX
CASE 751B05
ISSUE K
9
BP 8 PL
8 0.25 (0.010) M B S
TSEATING
PLANE
G
K
C
D 16 PL
0.25 (0.010) M T B S A S
R X 45_
F
MJ
SOLDERING FOOTPRINT
8X
6.40
16X 1.12
1 16
16X
0.58
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
1.27
PITCH
89
DIMENSIONS: MILLIMETERS
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