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MC74HC112A PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 MC74HC112A
部品説明 Dual J-K Flip-Flop
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 

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MC74HC112A Datasheet, MC74HC112A PDF,ピン配置, 機能
MC74HC112A
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Dual J-K Flip-Flop with
Set and Reset
HighPerformance SiliconGate CMOS
The MC74HC112A is identical in pinout to the LS112. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Each flipflop is negativeedge clocked and has activelow
asynchronous Set and Reset inputs.
The HC112A is identical in function to the HC76, but has a different
pinout.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Similar in Function to the LS112 Except When Set and Reset are
Low Simultaneously
Chip Complexity: 100 FETs or 25 Equivalent Gates
PbFree Packages are Available*
16
1
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
MC74HC112AN
AWLYYWWG
1
16
1
16
1
16
SOIC16
D SUFFIX
CASE 751B
HC112AG
AWLYWW
1
TSSOP16
DT SUFFIX
CASE 948F
16
HC
112A
ALYWG
G
1
16
1
SOEIAJ16
F SUFFIX
CASE 966
16
74HC112A
ALYWG
1
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = PbFree Package
G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
December, 2009 Rev. 7
1
Publication Order Number:
MC74HC112/D

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