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ADP3208C の電気的特性と機能

ADP3208CのメーカーはON Semiconductorです、この部品の機能は「CPU Synchronous Buck Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADP3208C
部品説明 CPU Synchronous Buck Controller
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 




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ADP3208C Datasheet, ADP3208C PDF,ピン配置, 機能
Preliminary
7-Bit,Programmablwwew.D,ataSDheetu4U.caom l-
Phase,Mobile,CPU,Synchronous
Buck Controller
ADP3208C
FEATURES
Single-chip solution
Fully compatible with the Intel® IMVP-6+™ specifications
Integrated MOSFET drivers
Input Voltage Range of 3.3 V to 22 V
Selectable 1- or 2-phase operation with up to 1 MHz per
phase switching frequency
Guaranteed ±8 mV worst-case differentially sensed core
voltage error over temperature
Automatic power-saving mode maximizes efficiency with
light load during deeper sleep operation
Soft transient control reduces inrush current and audio noise
Active current balancing between output phases
Independent current limit and load line setting inputs for
additional design flexibility
Built-in power-good blanking supports
voltage identification (VID) on-the-fly transients
7-bit, digitally programmable DAC with 0.3 V to 1.5 V output
Short-circuit protection with latch-off delay
Clock enable output delays the CPU clock until the core
voltage is stable
Output load current monitor
48-lead LFCSP
APPLICATIONS
Notebook power supplies for next-generation Intel processors
GENERAL DESCRIPTION
The ADP3208C is a highly efficient, multiphase, synchronous
buck switching regulator controller. With its integrated drivers,
the ADP3208C is optimized for converting the notebook
battery voltage into the core supply voltage required by high
performance Intel processors. An internal 7-bit DAC is used to
read a VID code directly from the processor and to set the CPU
core voltage to a value within the range of 0.3 V to 1.5 V. The
phase relationship of the output signals ensures interleaved 2-
phase operation.
The ADP3208C uses a multimode architecture run at a
programmable switching frequency and optimized for efficiency
depending on the output current requirement. The ADP3208C
switches between single- and dual-phase operation to maximize
efficiency with all load conditions. The chip includes a
programmable load line slope function to adjust the output voltage
as a function of the load current so that the core voltage is always
optimally positioned for a load transient. The ADP3208C also
provides accurate and reliable short-circuit protection,
adjustable current limiting, and a delayed power-good output.
The IC supports on-the-fly output voltage changes requested by
the CPU.
The ADP3208C is specified over the extended commercial
temperature range of -10°C to 100°C and is available in a 48-lead
LFCSP.
May 2008– Rev. 1

1 Page





ADP3208C pdf, ピン配列
TABLE OF CONTENTS
Features ...............................................................................................1
Applications .......................................................................................1
General Description..........................................................................1
Functional Block Diagram ...............................................................2
Revision History................................................................................3
Specifications .....................................................................................4
Timing Diagram................................................................................9
Absolute Maximum Ratings ..........................................................10
ESD Caution ................................................................................10
Pin Configuration and Function Descriptions ...........................11
Test Circuits .....................................................................................13
Typical Performance Characteristics............................................15
Theory of Operation .......................................................................19
Number of Phases .......................................................................19
Operation Modes ........................................................................19
Differential Sensing of Output Voltage ....................................22
Output Current Sensing .............................................................22
Active Impedance Control Mode..............................................22
CURRENT Control Mode AND THERMAL BALANCE ....23
Voltage Control Mode ................................................................23
Power-Good Monitoring............................................................23
Power-Up Sequence and Soft Start ...........................................23
Soft Transient...............................................................................24
Current Limit...............................................................................24
Changing VID on the Fly...........................................................25
REVISION HISTORY
5/08- Rev 1: Initial Preliminary Version
ADP3208Cwww.DataSheet4U.com
OUTPUT CROWBAR ...............................................................26
Reverse Voltage Protection ........................................................27
Output Enable and UVLO.........................................................27
Thermal Throttling Control ......................................................27
CURRENT MONITOR FUNCTION ......................................27
Application Information ................................................................31
Setting the Clock Frequency for PWM....................................31
Setting the Switching Frequency for RPM Operation of Phase
1 .....................................................................................................31
Inductor Selection.......................................................................31
COUT Selection..............................................................................33
Power MOSFETs .........................................................................34
Ramp Resistor Selection.............................................................35
COMP Pin Ramp ........................................................................35
Current Limit Setpoint...............................................................36
Output Current monitor ............................................................36
Feedback Loop Compensation Design ....................................36
CIN Selection and Input Current di/dt Reduction ..................37
Selecting Thermal Monitor Components................................38
Tuning Procedure for ADP3208C ............................................38
Layout and Component Placement ..........................................39
Outline Dimension .........................................................................41
Ordering Guide ...........................................................................41
Rev. 1 | Page 3 of 41 | www.onsemi.com


3Pages


ADP3208C 電子部品, 半導体
ADP3208C
www.DataSheet4U.com
Parameter
PULSE WIDTH
MODULATOR
CLOCK OSCILLATOR
RT Voltage
PWM Clock Frequency
Range2
PWM Clock Frequency
Symbol
VRT
fCLK
fCLK
RAMP GENERATOR
RAMP Voltage
RAMP Current Range2
PWM COMPARATOR
PWM Comparator Offset2
RPM COMPARATOR
RPM Current
RPM Comparator Offset2
EPWM CLOCK SYNC
Trigger Threshold2
VRAMP
IRAMP
VOSRPM
IRPM
VOSRPM
SWITCH AMPLIFIER
SW Common Mode Range2
SW Resistance
ZERO CURRENT SWITCHING
COMPARATOR
SW ZCS Threshold
Masked Off-Time
SYSTEM I/O BUFFERS
VID[6:0], PSI# INPUTS
Input Voltage
VSW(X)CM
RSW_PGND(X)
VDCM(SW1)
tOFFMSKD
Input Current
VID Delay Time2
DPRSLP
Input Voltage
Input Current
Conditions
Min Typ
Max Units
VARFREQ = high, RT = 125 kΩ, VVID = 1.5000 V
VARFREQ = low
See also VRT(VVID) formula
Operating Range
TA = +25°C, VVID = 1.2000 V
RT = 73 kΩ
RT = 125 kΩ
RT = 180 kΩ
EN = high, IRAMP = 30 μA
EN = low
EN = high
EN = low, RAMP = 19 V
VRAMP − VCOMP
VVID = 1.2 V, RT = 125 kΩ, VARFREQ = High
See also IRPM(RT) formula
VCOMP − (1 +VRPM)
Relative to COMP sampled TCLK earlier
2-phase configuration
1-phase configuration
Operating Range for current sensing
Measured from SW to PGND
1.22 1.25
0.98 1
0.3
1.27 V
1.02 V
3 MHz
970 1270
705 830
500 600
1570
955
700
kHz
kHz
kHz
0.9 1
VIN
1
−0.5
1.1 V
V
100 μA
+0.5 μA
−3 3 mV
−8.8 μA
−3 3 mV
400
450
−600
3
mV
mV
+200 mV
DCM mode, DPRSLP = 3.3 V
Measured from DRVH neg edge to DRVH pos edge
at max frequency of operation
−6
700
mV
ns
Refers to driving signal level
Logic low, Isink ≥ 1 μA
Logic high, Isource ≤ −5 μA
V = 0.2 V
VID[6:0], DPRSLP (active pull down to GND)
PSI# (active pull-up to VCC)
Any VID edge to FB change 10%
Refers to driving signal level
Logic low, Isink > 1 μA
Logic high, Isource < -5 μA
DPRSLP = low
DPRSLP = high
Rev. 1 | Page 6 of 41 | www.onsemi.com
0.7
−1
+1
200
0.3 V
V
μA
μA
ns
2.3
−1
+2
1.0 V
V
μA
μA

6 Page



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共有リンク

Link :


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