PDF DS92LV0422 Data sheet ( Hoja de datos )

Número de pieza	DS92LV0422
Descripción	10 - 75 MHz Channel Link II Serializer/Deserializer
Fabricantes	National Semiconductor
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No Preview Available ! DS92LV0421 / DS92LV0422 www.DataSheet4U.com PRELIMINARY May 26, 2010 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface General Description The DS92LV0421 (serializer) and DS92LV0422 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized inter- face over a single CML pair. The DS92LV0421 and DS92LV0422 enable applications that currently use the popular Channel Link or Channel Link style devices to seamlessly upgrade to an embedded clock inter- face to reduce interconnect cost or ease design challenges. The parallel LVDS interface also reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces. Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables longer dis- tance transmission over lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” operation. The DS92LV0421 and DS92LV0422 are programmable though an I2C interface as well as by pins. A built-in AT- SPEED BIST feature validates link integrity and may be used for system diagnostics. The DS92LV0421 and DS92LV0422 can be used inter- changeably with the DS92LV2421 or DS92LV2422. This al- lows designers the flexibility to connect to the host device and receiving devices with different interface types, LVDS or LVC- MOS. Features ■ 5-channel (4 data + 1 clock) Channel Link LVDS parallel interface supports 24-bit data 3-bit control at 10 – 75 MHz ■ AC Coupled STP Interconnect up to 10 meters in length ■ Integrated serial CML terminations ■ AT–SPEED BIST Mode and status pin ■ Optional I2C compatible Serial Control Bus ■ Power Down Mode minimizes power dissipation ■ 1.8V or 3.3V compatible control pin interface ■ >8 kV ESD (HBM) protection ■ -40° to +85°C temperature range SERIALIZER – DS92LV0421 ■ Data scrambler for reduced EMI ■ DC–balance encoder for AC coupling ■ Selectable output VOD and adjustable de-emphasis DESERIALIZER – DS92LV0422 ■ Random data lock; no reference clock required ■ Adjustable input receiver equalization ■ EMI minimization on output parallel bus (Spread Spectrum Clock Generation and LVDS VOD select) Applications ■ Embedded Video and Display ■ Machine Vision, Industrial Imaging, Medical Imaging ■ Office Automation — Printers, Scanners, Copiers ■ Security and Video Surveillance ■ General purpose data communication Applications Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation 301209 30120927 www.national.com 1 page DS92LV0422 Pin Diagram www.DataSheet4U.com DS92LV0422 — Top View 30120971 DS92LV0422 Pin Descriptions Pin Name Pin # I/O, Type Channel Link II Serial Interface RIN++ 40 I, CML RIN- 41 I, CML Channel Link Parallel Output Interface RxIN[3:0]+ 15, 19, 21, 23 O, LVDS RxIN[3:0]- 16, 20, 22, 24 O, LVDS RxCLKIN+ 17 O, LVDS RxCLKIN- 18 O, LVDS Description True Input. The output must be AC Coupled with a 0.1 μF capacitor. Inverting Input. The output must be AC Coupled with a 0.1 μF capacitor. True LVDS Data Output This pair should have a 100 Ω termination for standard LVDS levels. Inverting LVDS Data Output This pair should have a 100 Ω termination for standard LVDS levels. True LVDS Clock Output This pair should have a 100 Ω termination for standard LVDS levels. Inverting LVDS Clock Output This pair should have a 100 Ω termination for standard LVDS levels. 5 www.national.com 5 Page Symbol IDDZ IDDTXZ IDDIOZ Parameter Supply Current Power Down Conditions Pin/Freq. PDB = 0V, All other LVCMOS Inputs = 0V VDD = 1.89 V All VDD(1:8) pins VDDTX = 3.6 V VDDTX VDDIO = 1.89 VDDIO V VDDIO = 3.6V Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions DS92LV0421 CHANNEL LINK PARALLEL LVDS INPUT tRSP0 tRSP1 tRSP2 tRSP3 tRSP4 tRSP5 tRSP6 RJIT Receiver Strobe Position-bit 0 Receiver Strobe Position-bit 1 Receiver Strobe Position-bit 2 Receiver Strobe Position-bit 3 Receiver Strobe Position-bit 4 RxCLKIN = 75 MHz, RxIN[3:0] Figure 5 Receiver Strobe Position-bit 5 Receiver Strobe Position-bit 6 RxCLKIN Cycle-to-Cycle Jitter (Input clock requirement) DS92LV0422 CHANNEL LINK PARALLEL LVDS OUTPUT tLHT tTHLT tDCCJ Low to High Transition Time High to Low Transition Time Cycle-to-Cycle Output Jitter RL = 100Ω TxCLKOUT± = 10 MHz TxCLKOUT± = 75MHz tTTP1 Transmitter Pulse Position for 10 – 75 MHz bit 1 tTTP0 Transmitter Pulse Position for bit 0 tTTP6 Transmitter Pulse Position for bit 6 tTTP5 Transmitter Pulse Position for bit 5 tTTP4 Transmitter Pulse Position for bit 4 tTTP3 Transmitter Pulse Position for bit 3 tTTP2 Transmitter Pulse Position for bit 2 tSD tTPDD Delay-Latency Power Down Delay Active to OFF 75 MHz tTXZR Enable Delay OFF to Active 75 MHz DS92LV0421 Channel Link II CML OUTPUT tHLT Output Low-to-High Transition RL = 100Ω, De-emphasis = disabled, Time VODSEL = 0 Figure 3 RL = 100Ω, De-emphasis = disabled, VODSEL = 1 Min Min TBD TBD TBD TBD TBD TBD TBD 100 100 www.DataSheet4U.com Typ Max Units TBD TBD mA TBD TBD TBD TBD mA mA TBD TBD mA Typ Max Units 1.1 TBD 3.3 TBD 5.5 TBD 7.7 TBD 9.9 TBD 12.1 TBD 14.3 TBD TBD ns ns ns ns ns ns ns ns 0.3 0.6 0.3 0.6 900 2100 75 125 0 1 2 3 4 5 6 TBD 6 TBD 10 40 55 ns ns ps ps UI UI UI UI UI UI UI ns ns ns 200 300 ps 200 300 ps 11 www.national.com 11 Page

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