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H5DU1262GTR の電気的特性と機能

H5DU1262GTRのメーカーはHynix Semiconductorです、この部品の機能は「128Mb DDR SDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 H5DU1262GTR
部品説明 128Mb DDR SDRAM
メーカ Hynix Semiconductor
ロゴ Hynix Semiconductor ロゴ 




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H5DU1262GTR Datasheet, H5DU1262GTR PDF,ピン配置, 機能
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128Mb DDR SDRAM
H5DU1262GTR
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / May 2009
1

1 Page





H5DU1262GTR pdf, ピン配列
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H5DU1262GTR Series
DESCRIPTION
The H5DU1262GTR is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main
memory applications which requires large memory density and high bandwidth.
This Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
• VDD, VDDQ = 2.3V min ~ 2.7V max
(Typical 2.5V Operation +/- 0.2V for DDR266, 333
,400 and 500)
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• On chip DLL align DQ and DQS transition with CK
transition
• DM mask write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
• Programmable CAS latency 2/2.5 (DDR266, 333)
and 3/4 (DDR400, 500) supported
• Programmable burst length 2/4/8 with both sequen-
tial and interleave mode
• Internal four bank operations with single pulsed
/RAS
• Auto refresh and self refresh supported
• tRAS lock out function supported
• 4096 refresh cycles/64ms
• 66pin TSOP-II Lead-free and Halogen-free
• ROHS Compliant
ORDERING INFORMATION
OPERATING FREQUENCY
Part No.
H5DU1262GTR-XXX
Configuration Package
8Mx16
66TSOP-II
Grade
- FA
- FB
- E3
- E4
- J3
- K2
- K3
Clock Rate
250MHz@CL4
250MHz@CL4
200MHz@CL3
200MHz@CL3
133MHz@CL2
Remark
DDR500 (4-4-4)
DDR500 (4-3-3)
DDR400 (3-3-3)
DDR400 (3-4-4)
DDR333 (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
Rev. 1.0 / May 2009
3


3Pages


H5DU1262GTR 電子部品, 半導体
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H5DU1262GTR Series
Functinal Block Diagram (8M x16)
4Banks x 2Mbit x 16I/O Double Data Rate Syncronous DRAM
Write Data Register
2-RbMegiotidstePerrefetch Unit
32
16
DS
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
LDM
UDM
A0
A1
Amax
BA0
BA1
Command
Decoder
Address
Buffer
Bank
Control
Mode
Register
Row
Decoder
2Mx16 BANK 3
2Mx16 BANK 2
2Mx16 BANK 1
2Mx16 BANK 0
Memory
Cell
Array
32
DQ0
16
DQ15
Column Address
Decoder
CLK,
/CLK
Column
Decoder
CLK_DLL
DLL
Block
LDQS,
UDQS
Data Strobe
Transmitter
Data Strobe
Receiver
LDQS,
UDQS
Mode
Register
Rev. 1.0 / May 2009
6

6 Page



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部品番号部品説明メーカ
H5DU1262GTR

128Mb DDR SDRAM

Hynix Semiconductor
Hynix Semiconductor


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