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EP80579 の電気的特性と機能

EP80579のメーカーはIntelです、この部品の機能は「Integrated Processor Product Line」です。


製品の詳細 ( Datasheet PDF )

部品番号 EP80579
部品説明 Integrated Processor Product Line
メーカ Intel
ロゴ Intel ロゴ 




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EP80579 Datasheet, EP80579 PDF,ピン配置, 機能
www.DataSheet4U.com
Intel® EP80579 Integrated Processor
Product Line
Datasheet
Order Number: 320066-003US
August 2009

1 Page





EP80579 pdf, ピン配列
www.DataSheet4U.com
Product Features
„ System on a Chip (SoC)
— Integrated Intel® Architecture (IA) processor
and chipset (MCH/ICH) technology
— Extensive integration of standard Intel
architecture communications interfaces
provide cost, power and board area savings
(Gigabit Ethernet (GbE), Time Division
Multiplexing (TDM)processing, Security
Services Unit (SSU),and Acceleration
Services Units (ASU))
„ SKU Support1
— Embedded: Intel architecture compatibility
and high-speed interfaces (GbEs, PCI
Express*)
— Application Services: Security — Packet
security compatibility and IP Telephony packet
security, TDM, and High-Level Data Link
Control (HDLC)
„ Intel Architecture Processor
— Low-power and high-performance architecture
based on Intel Architecture (IA-32) processor
— Three operating frequency SKUs:
- 600 MHz, 1066 MHz, or 1200 MHz
— 256 KB L2 data coherent cache (2 way)
„ Integrated Memory Control Hub (IMCH) and
Integrated I/O Control Hub (IICH) Compatible
— Enhanced DMA (EDMA) controller
— Two SATA Gen1 or Gen2 interfaces
— Two USB 1.1 or USB 2.0 ports
— Two integrated, 16550-compatible UARTs
— LPC 1.1 interface
— Serial Peripheral Interface (SPI)
— Two SMBus 2.0 compliant interfaces
— GPIOs
— Watchdog Timer
— One 32/64-bit and two 32-bit high-precision
event timers
„ Acceleration Services Unit (ASU)
— High performance accelerator on-chip engines
for packet processing
— Support capabilities for commonly used
protocol implementations such as TCP/IP, UDP,
IPSec, SSL, NAT, and SRTP
„ Security Services Unit (SSU)
— High-performance on-chip Crypto Accelerator
— Support capabilities for commonly used
cryptographic protocol implementations
„ Single-Channel Double-Data-Rate (DDR)
SDRAM Memory
— Supports DDR2 at 400/533/667/800 MT/s
— Supports 32 or 64-bit interfaces
— Error correction code (ECC); single-bit correct/
double-bit detect (SEC/DED) coverage
— Addressable from Intel architecture processor
and PCI Express
„ Three Gigabit Ethernet MACs
— Three 10/100/1000 ports with RGMII/RMII
interfaces
— MDIO interface for external PHY configuration
— Serial EEPROM interface supports network
boot and wake-on LAN
„ Industry Standard PCI Express Interface
— Supports 1x8, 2x4, or 2x1 configurations as a
root complex
„ Integrated Serial ATA (SATA) Host Controllers
— Independent DMA operation on two ports
— Data transfer rates up to 3.0 Gb/s
— Alternate Device ID
„ Integrated High-speed Serial Interface (TDM)
— Supports up to 12 external T1/E1 and codecs
— Supports up to 128 HDLC channels
„ Local Expansion Bus (LEB)
— Supports up to eight chip selects
— 25-bit address and 16-bit data
— Supports HPI-8 and HPI-16
„ Dual Controller Area Network (CAN)
— Supports two CAN 2.0b interfaces
„ Single Synchronous Serial Port (SSP)
Compatible
„ IEEE 1588-2008 Hardware Assistance
— Supports two GbE and two CAN interfaces
— Time master/target support
„ 1088-Ball FCBGA package
— Dimensions of 37.5 mm x 37.5 mm
— 1.092-mm solder ball pitch
— Lead-free only — RoHS 5/6 compliant
„ Typical Applications
— Embedded, Security and/or IP Telephony
applications
† Intel recommends using the SPI for Pre-boot firmware
due to the reduced availability of LPC FWH.
‡ Feature must be enabled with EP80579 software. Refer
to the EP80579 software documentation for more
information.
1. For complete information about product features and SKUs, please refer to Chapter 47.0, “SKUs, Power Savings and Pre-Boot
Firmware”.
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
3


3Pages


EP80579 電子部品, 半導体
www.DataSheet4U.com
Contents
7.1.1 Register Description Tables ...................................................................... 183
7.1.2 Register Field Access Attributes ................................................................ 189
7.1.3 Register Nomenclature and Values ............................................................ 189
7.1.4 “Sticky” Register Fields............................................................................ 190
7.2 IA-32 core Registers ........................................................................................ 190
7.3 IMCH and IICH Registers .................................................................................. 191
7.3.1 IMCH Registers: Bus 0, Device 0, Function 0 ............................................. 191
7.3.2 IMCH Error Reporting Registers: Bus 0, Device 0, Function 1 ........................ 195
7.3.3 EDMA Engine Registers: Bus 0, Device 1, Function 0 ................................... 197
7.3.4 PCI Express* Port A Registers: Bus 0, Device 2, Function 0 ......................... 200
7.3.5 PCI Express* Port A1 Registers: Bus 0, Device 3, Function 0 ........................ 203
7.3.6 USB (1.1) Controller: Bus 0, Device 29, Functions 0 ................................... 206
7.3.7 USB (2.0) Controller: Bus 0, Device 29, Function 7 .................................... 207
7.3.8 Root Complex: Bus 0, Device 31, Function 0 ............................................. 209
7.3.9 LPC Interface: Bus 0, Device 31, Function 0 .............................................. 210
7.3.10 SATA Controller: Bus 0, Device 31, Function 2............................................ 213
7.3.11 SMBus Controller: Bus 0, Device 31, Function 3.......................................... 216
7.3.12 IA-32 Core Interface I/O-Mapped Register ................................................. 217
7.3.13 IMCH PCI Configuration ........................................................................... 217
7.3.14 APIC ..................................................................................................... 217
7.3.15 8259 Interrupt Controller (PIC) ................................................................ 219
7.3.16 APM Power Management.......................................................................... 219
7.3.17 LPC DMA ............................................................................................... 220
7.3.18 8254 Timers .......................................................................................... 221
7.3.19 High Precision Event Timers ..................................................................... 222
7.3.20 Watchdog Timer and Serial I/O................................................................. 222
7.3.21 Real Time Clock...................................................................................... 223
7.4 AIOC Registers ................................................................................................ 224
7.4.1 PCI-to-PCI Bridge: Bus 0, Device 4, Function 0........................................... 224
7.4.2 Gigabit Ethernet MAC: Bus M, Devices 0, 1, and 2, Function 0 ..................... 226
7.4.3 GCU: Bus M, Device 3, Function 0............................................................. 240
7.4.4 CAN Interface: Bus M, Device 4 and 5, Function 0 ...................................... 242
7.4.5 SSP Interface: Bus M, Device 6, Function 0 ............................................... 245
7.4.6 IEEE 1588 Timestamp Unit: Bus M, Device 7, Function 0 ............................. 247
7.4.7 Local Expansion Bus Interface: Bus M, Device 8, Function 0: ....................... 249
IA-32 Core and Integrated Memory Controller Hub,
Volume 2 of 6.............................................................................. 251
8.0 IA-32 Core ............................................................................................................. 253
8.1 Overview ........................................................................................................ 253
8.2 Theory of Operation ......................................................................................... 253
8.2.1 L2 Cache Size ........................................................................................ 253
8.2.2 Platform and JTAG Identifiers ................................................................... 253
8.2.3 FSB Physical Interface ............................................................................. 254
8.2.4 IA-32 Core and FSB Frequency ................................................................. 254
9.0 CMI Introduction ................................................................................................... 255
9.1 System Architecture......................................................................................... 256
9.2 PCI Express*................................................................................................... 256
9.2.1 Supported PCI Express Configurations ....................................................... 257
9.2.1.1 Low power SKU with PCI Express ports removed ................................. 257
9.3 Supported Debug and Management Interfaces ..................................................... 257
9.4 Supported IMCH Integrated Features.................................................................. 257
9.4.1 EDMA Controller ..................................................................................... 257
Intel® EP80579 Integrated Processor Product Line Datasheet
6
August 2009
Order Number: 320066-003US

6 Page



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部品番号部品説明メーカ
EP80579

Integrated Processor Product Line

Intel
Intel


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