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PDF HD6433037F Data sheet ( Hoja de datos )
| Número de pieza | HD6433037F | |
| Descripción | 16-Bit Single-Chip Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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REJ09B0353-0300
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
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16
H8/3039 ,Group H8/3039F-ZTAT™
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family / H8/300H Series
H8/3039 HD64F3039F
HD64F3039TE
HD64F3039VF
HD64F3039VTE
HD6433039F
HD6433039TE
HD6433039VF
HD6433039VTE
H8/3038 HD6433038F
HD6433038TE
HD6433038VF
HD6433038VTE
H8/3037 HD6433037F
HD6433037TE
HD6433037VF
HD6433037VTE
H8/3036 HD6433036F
HD6433036TE
HD6433036VF
HD6433036VTE
Rev.3.00
Revision date: Mar. 26, 2007
www.renesas.com
1 page  
Preface
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The H8/3039 Group comprises high-performance single-chip microcomputers (MCUs) that
integrate system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities. Of the two SCI
channels, one has been expanded to support the ISO/IEC 7816-3 smart card interface. Functions
have also been added to reduce power consumption in battery-powered applications: individual
modules can be placed in standby, and the frequency of the system clock supplied to the chip can
be divided down under software control.
The five MCU operating modes offer a choice of expanded mode, single-chip mode, and address
space size, enabling the H8/3039 Group to adapt quickly and flexibly to a variety of conditions.
In addition to its mask-ROM versions, the H8/3039 Group has an F-ZTAT™ version with user
programmable on-chip flash memory that can be programmed on-board. These versions enable
users to respond quickly and flexibly to changing application specifications.
This manual describes the H8/3039 Group hardware. For details of the instruction set, refer to the
H8/300H Series Software Manual.
Note: F-ZTAT is a trademark of Renesas Technology Corp.
Rev.3.00 Mar. 26, 2007 Page v of xxii
REJ09B0353-0300
5 Page 
Contents
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Section 1 Overview .............................................................................................................
1.1 Overview...........................................................................................................................
1.2 Block Diagram ..................................................................................................................
1.3 Pin Description..................................................................................................................
1.3.1 Pin Arrangement ..................................................................................................
1.3.2 Pin Functions .......................................................................................................
1.4 Pin Functions ....................................................................................................................
1
1
6
7
7
8
12
Section 2 CPU ...................................................................................................................... 17
2.1 Overview........................................................................................................................... 17
2.1.1 Features................................................................................................................ 17
2.1.2 Differences from H8/300 CPU............................................................................. 18
2.2 CPU Operating Modes ...................................................................................................... 19
2.3 Address Space ................................................................................................................... 20
2.4 Register Configuration ...................................................................................................... 21
2.4.1 Overview.............................................................................................................. 21
2.4.2 General Registers ................................................................................................. 22
2.4.3 Control Registers ................................................................................................. 23
2.4.4 Initial CPU Register Values ................................................................................. 24
2.5 Data Formats ..................................................................................................................... 25
2.5.1 General Register Data Formats ............................................................................ 25
2.5.2 Memory Data Formats ......................................................................................... 27
2.6 Instruction Set ................................................................................................................... 28
2.6.1 Instruction Set Overview ..................................................................................... 28
2.6.2 Instructions and Addressing Modes ..................................................................... 29
2.6.3 Tables of Instructions Classified by Function...................................................... 31
2.6.4 Basic Instruction Formats .................................................................................... 40
2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... 41
2.7 Addressing Modes and Effective Address Calculation ..................................................... 41
2.7.1 Addressing Modes ............................................................................................... 41
2.7.2 Effective Address Calculation ............................................................................. 45
2.8 Processing States............................................................................................................... 49
2.8.1 Overview.............................................................................................................. 49
2.8.2 Program Execution State...................................................................................... 49
2.8.3 Exception-Handling State .................................................................................... 50
2.8.4 Exception-Handling Sequences ........................................................................... 51
2.8.5 Reset State............................................................................................................ 53
Rev.3.00 Mar. 26, 2007 Page xi of xxii
REJ09B0353-0300
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD6433037F.PDF ] | |
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