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PDF TDA10023HT Data sheet ( Hoja de datos )
| Número de pieza | TDA10023HT | |
| Descripción | Single chip DVB-C/MCNS channel receiver | |
| Fabricantes | Philips | |
| Logotipo |  |
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TDA10023HT
Single chip DVB-C/MCNS channel receiver
Rev. 01 — 12 April 2005
Product data sheet
1. General description
The TDA10023HT is a single chip DVB-C/MCNS channel receiver for 4, 16, 32, 64, 128
and 256-QAM modulated signals. The device interfaces directly to the IF signal, which is
sampled by a 10-bit A/D converter.
The TDA10023HT performs the clock and the carrier recovery functions. The digital loop
filters for both clock and carrier recovery are programmable in order to optimize their
characteristics according to the current application.
After baseband conversion, equalization filters are used for echo cancellation in cable
applications. These filters are configured as T-spaced transversal equalizer or DFE
equalizer, so that the system performance can be optimized according to the network
characteristics. A proprietary equalization algorithm, independent of carrier offset, is
achieved in order to assist carrier recovery. Then a decision directed algorithm takes
place, to achieve final equalization convergence.
The TDA10023HT chip implements two FEC decoders, one for each standard. In the
DVB-C mode the TDA10023HT implements a Forney convolutional de-interleaver of depth
12 blocks and a Reed-Solomon decoder which corrects up to 8 erroneous bytes. The
de-interleaver and the Reed-Solomon decoder are automatically synchronized thanks to
the frame synchronization algorithm that uses the MPEG2 sync byte. Finally descrambling
according to DVB-C standard is achieved at the Reed-Solomon output. In the MCNS
mode the receiver error correction implements a soft decision trellis decoder to correct
random channel errors, a randomizer, a convolutional de-interleaver of depth I = 128, 64,
32, 16, 8 and J = 1, 2, 3, 4, 8, 16 for burst protection, and a Reed-Solomon decoder which
corrects up to 3 erroneous symbols. The de-interleaver and the Reed-Solomon decoder
are automatically synchronized using the frame sync trailer.
This device is controlled via an I2C-bus.
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VDDA1
XIN XOUT
23
1
VSSA1
4
VDDD3
3
7, 24, 41
VSSD3
3
8, 25, 42
VDDD2
3
14, 30, 43
VSSD2
3
15, 31, 44
VDDD1
50
VSSD1
49
VDDA2
61
VDDA3
55
VSSA3
59
VDDD4
60
SACLK
5
PLL
10
IF ADC
GPIO
29
CTRL
32
GPIO
TEST
CLRB
VIP
VIM
IICDIV
6
16
58
57
10
SDA
SCL
18
17
CLOCK
RECOVERY
BASEBAND
CONVERSION
DECIMATION
FILTERS
TIMING
INTERPOLATOR
HALF
NYQUIST
AGC
PWM
PWM
EQUALIZER
CARRIER
RECOVERY
9 AGCTUN
11 AGCIF
DECISION
DIFFERENTIAL
DECODER
TRELLIS
DEMODULATOR
DE-INTERLEAVER
RS
DECODER
DE-SCRAMBLER
FRAME
SYNC
DE-
RANDOMIZER
DE-
INTERLEAVER
REED
SOLOMON
DECODER
TDA10023HT
12
SADDR
I2C-BUS
INTERFACE
JQAM
FILTER
MPEG2
TS
CKSUM
8
OUTPUT
INTERFACE
37 to 40,
45 to 48
36
35
34
33
JTAG
28
27
22
23
26
21
19
20
13, 51, 52, 53, 54, 56, 62, 63, 64
n.c.
001aac555
DO[7:0]
DEN
OCLK
PSYNC
UNCOR
programmable
interface
TDO
TMS
TCK
TDI
TRST
ENSERI
SDAT
SCLT
serial
interface
Fig 1. Internal block diagram
5 Page 
Philips Semiconductors
www.DataSheet4U.com
TDA10023HT
Single chip DVB-C/MCNS channel receiver
9. Application information
9.1 General block diagram
VDDA2 VDDA3 VDDD1 VSSD2 VDDD3 VSSA3
VDDA1 VSSA1 VDDD4 VDDD2 VSSD1 VSSD3
33
33
ENSERI
TEST
CLRB
VIP
VIM
IICDIV
XIN XOUT
POWER SUPPLIES
INPUTS
TDA10023HT
I2C-BUS INTERFACES
PROGRAMMABLE
OUTPUT
AGCTUN
AGCIF
SACLK
8
DO[7:0]
DEN
OCLK
PSYNC
UNCOR
5 boundary scan
SERIAL OUTPUT
SADDR SCL SDA
Fig 3. General block diagram
SCLT SDAT CTRL GPIO
001aac557
9.2 Typical application
AGC1
CIRCUITRY
AGC2
CIRCUITRY
RF
input
TUNER
IF ANALOG
CIRCUITRY
I2C-bus tuner
AGCIF AGCTUN
XIN XOUT
OUTPUT1(1)
VIP
TDA10023HT
VIM
SCLT, SDAT
OUTPUT2(2)
SCL, SDA
DO [7:0]
DEN
OCLK
PSYNC
UNCOR
TDO (DO)
TMS (DEN)
TCK (OCLK)
TDI (PSYNC)
TRST (UNCOR)
I2C-bus
001aac558
(1) First output1 can be either a parallel output mode A, a parallel output mode B, a parallel output mode C, or a serial output
(programmable interface).
(2) Second output2 is a serial output (serial interface).
Fig 4. Front-end receiver schematic
9397 750 14559
Product data sheet
Rev. 01 — 12 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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