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IS41C16257A の電気的特性と機能

IS41C16257AのメーカーはIntegrated Silicon Solutionです、この部品の機能は「256K x 16 (4-MBIT) DYNAMIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS41C16257A
部品説明 256K x 16 (4-MBIT) DYNAMIC RAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS41C16257A Datasheet, IS41C16257A PDF,ピン配置, 機能
IS41C16257A
IS41LV16257A
256K x 16 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
ISSI®
www.DataSheet4U.com
APRIL 2005
FEATURES
• Fast access and cycle time
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode: RAS-Only, CAS-before-RAS (CBR),
and Hidden
• JEDEC standard pinout
• Single power supply:
-- 5V ± 10% (IS41C16257A)
-- 3.3V ± 10% (IS41LV16257A)
• Byte Write and Byte Read operation via two CAS
• Lead-free available
DESCRIPTION
The ISSI IS41C16257A and the IS41LV16257A are
262,144 x 16-bit high-performance CMOS Dynamic
Random Access Memories. Fast Page Mode allows
512 random accesses within a single row with access
cycle time as short as 12 ns per 16-bit word. The Byte
Write control, of upper and lower byte, makes these
devices ideal for use in 16- and 32-bit wide data bus
systems.
These features make the IS41C16257A and the
IS41LV16257A ideally suited for high band-width
graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The IS41C16257A and the IS41LV16257A are
packaged in a 40-pin, 400-mil SOJ and TSOP (Type II).
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. Fast Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
-35 -60 Unit
35 60 ns
11 15 ns
18 30 ns
14 25 ns
60 110 ns
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05
1

1 Page





IS41C16257A pdf, ピン配列
IS41C16257A
IS41LV16257A
ISSI®
TRUTH TABLE
www.DataSheet4U.com
Function
Standby
Read: Word
Read: Lower Byte
RAS LCAS UCAS WE OE Address tR/tC
H HHXX
X
L L L H L ROW/COL
L L H H L ROW/COL
Read: Upper Byte
L H L H L ROW/COL
Write: Word (Early Write)
Write: Lower Byte (Early Write)
L L L L X ROW/COL
L L H L X ROW/COL
Write: Upper Byte (Early Write)
L H L L X ROW/COL
Read-Write(1,2)
Hidden Refresh2)
RAS-Only Refresh
CBR Refresh(3)
L
Read LHL
Write LHL
L
HL
L
L
L
H
L
L HL LH ROW/COL
L H L ROW/COL
L L X ROW/COL
H X X ROW/NA
LXX
X
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
I/O
High-Z
DOUT
Lower Byte, DOUT
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DOUT
DIN
Lower Byte, DIN
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DIN
DOUT, DIN
DOUT
DOUT
High-Z
High-Z
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05
3


3Pages


IS41C16257A 電子部品, 半導体
IS41C16257A
IS41LV16257A
ISSI ®
www.DataSheet4U.com
ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max. Unit
IIL Input Leakage Current
Any input 0V < VIN < Vcc
Other inputs not under test = 0V
–10 10 µA
IIO Output Leakage Current
Output is disabled (Hi-Z)
0V < VOUT < Vcc
–10 10 µA
VOH Output High Voltage Level
IOH = –2 mA
2.4 —
V
VOL Output Low Voltage Level
IOL = +2 mA
— 0.4
V
ICC1 Stand-by Current: TTL
RAS, LCAS, UCAS VIH
Com. 5V —
4 mA
ICC1 Stand-by Current: TTL
RAS, LCAS, UCAS VIH
Com. 3.3V —
4 mA
ICC2 Stand-by Current: CMOS
RAS, LCAS, UCAS VCC – 0.2V
5V —
2 mA
ICC2 Stand-by Current: CMOS
RAS, LCAS, UCAS VCC – 0.2V
3.3V —
1 mA
ICC3 Operating Current:
RAS, LCAS, UCAS,
-35 — 230 mA
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
-60 — 170
Average Power Supply Current
ICC4 Operating Current:
RAS = VIL, LCAS, UCAS,
Fast Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
ICC5 Refresh Current:
RAS-Only(2,3)
RAS Cycling, LCAS, UCAS VIH
tRC = tRC (min.)
Average Power Supply Current
-35 — 220 mA
-60 — 160
-35 — 230 mA
-60 — 170
ICC6 Refresh Current:
RAS, LCAS, UCAS Cycling
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-35 — 230 mA
-60 — 170
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper
device operation is assured.The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is
exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each fast page cycle.
5. Enables on-chip refresh and address counters.
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
04/22/05

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
IS41C16257

256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS41C16257-35K

256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS41C16257-35KI

256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS41C16257-35T

256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc


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