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PDF AD7643 Data sheet ( Hoja de datos )
| Número de pieza | AD7643 | |
| Descripción | 1.25 MSPS PulSAR ADC | |
| Fabricantes | Analog Devices | |
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18-Bit, 1.25 MSPS PulSAR ADC®www.DataSheet4U.com
AD7643
FEATURES
Throughput: 1.25 MSPS
INL: ±1.5 LSB typical, ±3 LSB maximum (±11 ppm of full scale)
18-bit resolution with no missing codes
Dynamic range: 95 dB typical
SINAD: 93.5 dB typical @ 20 kHz (VREF = 2.5 V)
THD: −113 dB typical @ 20 kHz (VREF = 2.5 V)
2.048 V internal reference: typical drift 8 ppm/°C; TEMP output
Differential input range: ±VREF (VREF up to 2.5 V)
No pipeline delay (SAR architecture)
Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 2.5 V supply operation
Power dissipation
65 mW typical @ 1.25 MSPS with internal REF
2 μW in power-down mode
Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ
Pin compatible with the AD7641 and other PulSAR ADC’s
APPLICATIONS
Medical instruments
High speed data acquisition/high dynamic data acquisition
Digital signal processing
Spectrum analysis
Instrumentation
Communications
ATE
GENERAL DESCRIPTION
The AD7643 is an 18-bit, 1.25 MSPS, charge redistribution
SAR, fully differential, analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. The part contains a
high speed, 18-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. The part has no
latency and can be used in asynchronous rate applications. The
AD7643 is hardware factory calibrated and tested to ensure ac
parameters, such as signal-to-noise ratio (SNR), in addition to
the more traditional dc parameters of gain, offset, and linearity.
The AD7643 is only available in Pb-free packages with
operation specified from −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND
DVDD DGND
AGND
AVDD
IN+
IN–
PDREF
PDBUF
PD
RESET
REF
REF AMP
SWITCHED
CAP DAC
AD7643
SERIAL
PORT 18
PARALLEL
INTERFACE
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
OVDD
OGND
D[17:0]
MODE0
MODE1
BUSY
RD
CS
D0/OB/2C
CNVST
Figure 1.
Table 1. PulSAR 48-Lead Selection
Type/kSPS
100 to
250
500 to
570
Pseudo
Differential
AD7651,
AD7660,
AD7661
AD7650,
AD7652,
AD7664,
AD7666
True Bipolar
AD7610, AD7665
AD7663
True
Differential
AD7675 AD7676
18-Bit
Multichannel/
Simultaneous
AD7631,
AD7678
AD7679
AD7654
650 to
1000
AD7653,
AD7667
AD7612,
AD7671
AD7677
AD7634,
AD7674
AD7655
>1000
AD7621,
AD7622,
AD7623
AD7641,
AD7643
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7643 is a 1.25 MSPS, charge redistribution,
18-bit SAR ADC.
2. Superior Linearity.
The AD7643 has no missing 18-bit code.
3. Internal Reference.
The AD7643 has a 2.048 V internal reference with a typical
drift of ±8 ppm/°C and an on-chip TEMP sensor.
4. Single-Supply Operation.
The AD7643 operates from a 2.5 V single supply.
5. Serial or Parallel Interface.
Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial
interface arrangement compatible with 2.5 V, 3.3 V, or
5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD7643
TIMING SPECIFICATIONS
www.DataSheet4U.com
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (Refer to Figure 30 and Figure 31)
Convert Pulse Width
Time Between Conversions
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Acquisition Time
RESET Pulse Width
RESET Low to BUSY High Delay2
BUSY High Time from RESET Low2
PARALLEL INTERFACE MODES (Refer to Figure 32 to Figure 35 )
CNVST Low to Data Valid Delay
Data Valid to BUSY Low Delay
Bus Access Request to Data Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES3 (Refer to Figure 36 and Figure 37)
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay3
CS Low to SDOUT Delay
CNVST Low to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period4
Internal SCLK High4
Internal SCLK Low4
SDOUT Valid Setup Time4
SDOUT Valid Hold Time4
SCLK Last Edge to SYNC Delay4
CS High to SYNC Hi-Z
CS High to Internal SCLK Hi-Z
CS High to SDOUT Hi-Z
BUSY High in Master Serial Read After Convert4
CNVST Low to SYNC Asserted Delay
SYNC Deasserted to BUSY Low Delay
SLAVE SERIAL INTERFACE MODES (Refer to Figure 39 and Figure 40)
External SCLK Set-Up Time
External SCLK Active Edge to SDOUT Delay
SDIN Set-Up Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
Symbol Min Typ
t1 15
t2 800
t3
t4
t5 1
t6 10
t7
t8 250
t9 15
t38 10
t39 500
t10
t11 2
t12
t13 2
t14
t15
t16
t17 135
t18 2
t19 8
t20 2
t21 2
t22 1
t23 0
t24 0
t25
t26
t27
t28 See Table 4
t29 508
t30 13
t31 5
t32 1
t33 5
t34 5
t35 12.5
t36 5
t37 5
Max Unit
701 ns
ns
23 ns
550 ns
ns
ns
550 ns
ns
ns
ns
ns
550 ns
ns
20 ns
15 ns
10 ns
10 ns
10 ns
ns
ns
20 ns
ns
ns
ns
ns
ns
10 ns
10 ns
10 ns
ns
ns
ns
ns
8 ns
ns
ns
ns
ns
ns
1 See the Conversion Control section.
2 See the Digital Interface section and the RESET section.
3 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
4 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
Rev. 0 | Page 5 of 28
5 Page 
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Gain Error
The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal negative full scale
(−2.0479922 V for the ±2.048 V range). The last transition
(from 111…10 to 111…11) should occur for an analog voltage
1½ LSB below the nominal full scale (+2.0479766 V for the
±2.048 V range). The gain error is the deviation of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.
Zero Error
The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
Dynamic Range
It is the ratio of the rms value of the full scale to the rms noise
measured with the inputs shorted together. The value for
dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
AD7643
www.DataSheet4U.com
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal to (Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
ENOB = [(SINADdB − 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
The time required for the AD7643 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Reference Voltage Temperature Coefficient
It is derived from the typical shift of output voltage at 25°C on a
sample of parts maximum and minimum reference output
voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is
expressed in ppm/°C using
( )TCVREF
(ppm/°C)
=
VREF (Max) −VREF
VREF (25°C)× TMAX
(Min)
− TMIN
×106
where:
VREF (Max) = Maximum VREF at TMIN, T(25°C), or TMAX
VREF (Min) = Minimum VREF at TMIN, T(25°C), or TMAX
VREF (25°C) = VREF at 25°C
TMAX = +85°C
TMIN = –40°C
Rev. 0 | Page 11 of 28
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| PDF Descargar | [ Datasheet AD7643.PDF ] | |
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