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PDF UPD70F3700 Data sheet ( Hoja de datos )
| Número de pieza | UPD70F3700 | |
| Descripción | 32-Bit Single-Chip Microcontrollers | |
| Fabricantes | NEC Electronics | |
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Preliminary User’s Manual
www.DataSheet4U.com
V850ES/HE2
32-Bit Single-Chip Microcontrollers
Hardware
µPD70F3700
µPD70F3701
Document No. U17720EJ1V0UD00 (1st edition)
Date Published January 2006 N CP(K)
Printed in Japan
2005
1 page  
PREFACE
www.DataSheet4U.com
Readers
Purpose
Organization
This manual is intended for users who wish to understand the functions of the
V850ES/HE2 and design application systems using the V850ES/HE2.
This manual is intended to give users an understanding of the hardware functions of
the V850ES/HE2 shown in the Organization below.
This manual is divided into two parts: Hardware (this manual) and Architecture
(V850ES Architecture User’s Manual).
Hardware
• Pin functions
• CPU function
• On-chip peripheral functions
• Flash memory programming
• Electrical specifications (target)
Architecture
• Data types
• Register set
• Instruction format and instruction set
• Interrupts and exceptions
• Pipeline operation
How to Read This Manual
It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the V850ES/HE2
→ Read this manual according to the CONTENTS.
To find the details of a register where the name is known
→ Use APPENDIX A REGISTER INDEX.
To understand the details of an instruction function
→ Refer to the V850ES Architecture User’s Manual available separately.
To know the electrical specifications of the V850ES/HE2
→ See CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET).
Register format
→ The name of the bit whose number is in angle brackets (<>) in the figure of the
register format of each register is defined as a reserved word in the device file.
The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note
with caution that if “xxx.yyy” is described as is in a program, however, the
compiler/assembler cannot recognize it correctly.
Preliminary User’s Manual U17720EJ1V0UD
5
5 Page 
11.6
11.7
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11.5.3 Operation mode....................................................................................................................... 402
11.5.4 Power-fail compare mode........................................................................................................ 406
Cautions .................................................................................................................................411
How to Read A/D Converter Characteristics Table............................................................415
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ..............................................419
12.1 Features..................................................................................................................................419
12.2 Configuration .........................................................................................................................420
12.3 Registers ................................................................................................................................422
12.4 Interrupt Request Signals.....................................................................................................428
12.5 Operation................................................................................................................................429
12.5.1 Data format.............................................................................................................................. 429
12.5.2 SBF transmission/reception format.......................................................................................... 431
12.5.3
12.5.4
12.5.5
SBF transmission .................................................................................................................... 433
SBF reception.......................................................................................................................... 434
UART transmission.................................................................................................................. 435
12.5.6
12.5.7
12.5.8
Continuous transmission procedure ........................................................................................ 436
UART reception ....................................................................................................................... 438
Reception errors ...................................................................................................................... 439
12.6
12.7
12.5.9 Parity types and operations ..................................................................................................... 441
12.5.10 Receive data noise filter .......................................................................................................... 442
Dedicated Baud Rate Generator ..........................................................................................443
Cautions .................................................................................................................................451
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) ....................................................452
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Features..................................................................................................................................452
Configuration .........................................................................................................................453
Registers ................................................................................................................................455
Interrupt Request Signals.....................................................................................................462
Operation................................................................................................................................463
13.5.1 Single transfer mode (master mode, transmission/reception mode)........................................ 463
13.5.2 Single transfer mode (master mode, reception mode)............................................................. 464
13.5.3 Continuous mode (master mode, transmission/reception mode)............................................. 465
13.5.4 Continuous mode (master mode, reception mode).................................................................. 466
13.5.5 Continuous reception mode (error).......................................................................................... 467
13.5.6 Continuous mode (slave mode, transmission/reception mode) ............................................... 468
13.5.7 Continuous mode (slave mode, reception mode) .................................................................... 469
13.5.8 Clock timing ............................................................................................................................. 470
Output Pin Status with Operation Disabled .......................................................................472
Operation Flow ......................................................................................................................473
Baud Rate Generator ............................................................................................................479
13.8.1 Baud rate generation ............................................................................................................... 480
13.9 Cautions .................................................................................................................................481
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION ...............................................482
Preliminary User’s Manual U17720EJ1V0UD
11
11 Page | ||
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