IS61LV256AL Datasheet PDF - Integrated Silicon Solution
| Part Number | IS61LV256AL | |
| Description | 32K x 8 LOW VOLTAGE CMOS STATIC RAM | |
| Manufacturers | Integrated Silicon Solution | |
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IS61LV256AL
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
ISSI®
MARCH 2006
FEATURES
• High-speed access times:
— 10 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 60 µW (typical) CMOS standby
— 65 mW (typical) operating
www.D•ataTSTheLect4oUm.cpomatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
• Lead-free available
DESCRIPTION
The ISSI IS61LV256AL is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using
ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
150 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE). The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS61LV256AL is available in the JEDEC standard 28-
pin, 300-mil SOJ and the 450-mil TSOP (Type I) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VDD
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
32K X 8
MEMORY ARRAY
COLUMN I/O
CE
OE
CONTROL
CIRCUIT
WE
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
1
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IS61LV256AL
ISSI®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
tRC Read Cycle Time
tAA Address Access Time
tOHA Output Hold Time
tACE CE Access Time
tDOE OE Access Time
tLZOE(2)
OE to Low-Z Output
www.DatatHSZhOeEe(2t4) U.comOE to High-Z Output
tLZCE(2)
CE to Low-Z Output
tHZCE(2)
CE to High-Z Output
tPU(3)
CE to Power-Up
tPD(3)
CE to Power-Down
-10 ns
Min. Max.
10 —
— 10
2—
— 10
—5
0—
—5
3—
—5
0—
— 10
-12 ns
Min. Max.
12 —
— 12
2—
— 12
—5
0—
—5
3—
—6
0—
— 12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
3.3V
319 Ω
3.3V
319 Ω
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
353 Ω
OUTPUT
5 pF
Including
jig and
scope
Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
353 Ω
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IS61LV256AL electronic component. |
| Information | Total 13 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IS61LV256AL.PDF Datasheet ] | |
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