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PDF IN16C1054 Data sheet ( Hoja de datos )
| Número de pieza | IN16C1054 | |
| Descripción | Quard Uart | |
| Fabricantes | IK Semicon | |
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TECHNICAL DATA
Quard Uart with 256-Byte FIFO
IN16C1054
1. Functional Description
IN16C1054 is a quad UART(Universal Asynchronous Receiver/Transmitter) with 256-byte FIFO supporting maximum
communication speed of 5.3Mbps. It offers flow control function by hardware or software and signal lines which can open
or close the Tx/Rx input/output when communicating by RS-422 or RS-485. It can handle four interrupt signals (INT0,
INT1, INT2 and INT3) with one global interrupt signal line (GINT) and offers a new ‘Xoff re-transmit’ function in addition to
Xon any character.
UART can convert 8-bit parallel data to asynchronous serial data and vice versa. It can transmit 5 to 8-bit letters, program
I/O interrupt trigger level and has 256-byte I/O data FIFO.
www.DaUtAaRShTeceat4nUg.ceonmerate any baud rate using clock and programmable divisor, transmit data with even, odd or no parity and 1,
1.5, 2 stop bit, and detect break, idle, framing error, FIFO overflow and parity error in input data.
UART has a software interface for modem controlling.
IN16C1054 offers TQFP80 and PLCC68 packages.
2. Features
• 4 Channel UART
• 3.3V Operation
• 5V Tolerant Inputs
• Pin-to-pin Compatible with Industry Standard
SB16C554 with Additional
• Enhancements
• Up to 5.3 Mbps Baud Rate (Up to 85 MHz Oscillator
Input Clock)
• 256-byte Transmit FIFO
• 256-byte Receive FIFO with Error Flags
• Industrial Temperature Range (-20 ℃ to +85 ℃)
• Programmable and Selectable Transmit and
Receive FIFO Trigger Levels for DMA
• and Interrupt Generation
• Software (Xon/Xoff) / Hardware (RTS#/CTS#) Flow
Control
- Programmable Xon/Xoff Characters
- Programmable Auto-RTS and Auto-CTS
• Global Interrupt Mask/Poll Control
• Optional Data Flow Resume by Xon Any Character
Control
• Optional Data Flow Additional Halt by Xoff Re-
transmit Control
• RS-422 Point to Point/Multi-Drop Control
• RS-485 Echo/Non Echo Control
• DMA Signaling Capability for Both Received and
Transmitted Data
• Software Selectable Baud Rate Generator
• Prescaler Provides Additional Divide-by-4 Function
• Fast Data Bus Access Time
• Programmable Sleep Mode
• Programmable Serial Interface Characteristics
- 5, 6, 7, or 8-bit Characters
- Even, Odd, or No Parity Bit Generation and
Detection
- 1, 1.5, or 2 Stop Bit Generation
• False Start Bit Detection
• Line Break Generation and Detection
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (RTS#, CTS#, DTR#,
DSR#, DCD#, and RI#)
Rev. 00
1 page  
IN16C1054
Table 2: Pin Description
Data Bus Interface
Name
Pin
TQFP80
A0 48
A1 47
A2 46
D0
D1
D2
www.DaDt3aSheet4U.com
D4
D5
D6
D7
7
8
9
11
12
13
14
15
IOR#
70
IOW#
CS0#
CS1#
CS2#
CS3#
INT0/GINT
INT1
INT2
INT3
31
28
33
68
73
27
34
67
74
INTSEL
6
PLCC68
34
33
32
66
67
68
1
2
3
4
5
52
18
16
20
50
54
15
21
49
55
65
5.3 Pin Description
Type Description
I Address Bus Lines [2:0]. These 3 address lines select one
I of the internal registers in UART channel 0-3 during a data
I bus transaction.
I/O Data Bus Lines [7:0]. These pins are tri-state data bus for
I/O data transfer to or from the controlling CPU.
I/O
I/O
I/O
I/O
I/O
I/O
I Read Data (active low strobe). A valid low level on IOR# will
load the data of an internal register defined by address lines
A [2:0] onto the UART data bus for access by an external
CPU.
I Write Data (active low strobe). A valid low level on IOW# will
transfer the data from external CPU to an internal register
that is defined by address lines A [2:0].
I Chip Select 0, 1, 2, and 3 (active low). These pins enable
I data transfers between the external CPU and the UART for
I the respective channel.
I
O Interrupt 0/Global Interrupt, Interrupt 1, 2, and 3. These pins
O provide individual channel interrupts or global interrupt.
O INT0-3 are enabled when MCR[3] is set to ‘1’ and AFR[4] is
O cleared to ‘0’ (default state). But INT0 operates as GINT and
INT1-INT3 are disabled when AFR[4] is set to ‘1’.
INT0-3’s asserted state is active high, but GINT’s asserted
state is determined by AFR[5]. GINT’s asserted state is
active high when AFR[5] is set to ‘1’, and active low when
AFR[5] is cleared to ‘0’.
I Interrupt Select. When INTSEL is left open or low state, the
tri-state interrupts available on INT0-3 are enabled by
MCR[3]. But, when INTSEL is in high state, INT0-3 are
always enabled.
Rev. 00
5 Page 
IN16C1054
www.DataSheet4U.com
6.3 Software Flow Control
Software flow control is performed by Xon and Xoff character transmitting/accepting.
Software flow control is enabled/disabled independently by programming EFR[3:0] and
MCR[6:5, 2]. If TX software flow control is enabled by EFR[3:2], Xoff character is
transmitted to report that data can not be accepted when the stored amount of data in
RX FIFO exceeds the value in FUR. After the CPU reads the data in RX FIFO and if the
read amount is less than the value in FLR, Xon character is transmitted to report that
more data can be accepted. If TX software flow control is enabled by EFR[1:0] and Xoff
character is inputted through RXD pin, it means no more data can be accepted, and
data transmission is suspended even though data are in TX FIFO. If Xon character is
received through RXD pin while data transmission is suspended, it means more data
can be accepted, and therefore data in TX FIFO are re-transmitted. These procedures
prevent overruns during communication. If software flow control is disabled, overrun
occurs when the transmit data rate exceeds RX FIFO service latency. Different
combinations of software flow control can be enabled by setting different combinations
of EFR[3:0] . Table 3 shows software flow control options.
Table 3: Software flow control options (EFR[3:0])
EFR[3] EFR[2] EFR[1]
00X
10X
01X
11X
XX0
XX1
XX0
XX1
000
001
000
001
100
101
100
101
010
011
010
011
110
111
110
111
EFR[0]
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TX, RX software flow controls
No transmit control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
Transmit Xon1, Xon2/Xoff1, Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Receiver compares Xon1, Xon2/Xoff1, Xoff2
No transmit control, No receive flow control
No transmit control, Receiver compares Xon1/Xoff1
No transmit control, Receiver compares Xon2/Xoff2
No transmit control, Receiver compares Xon1, Xon2/Xoff1, Xoff2
Transmit Xon1/Xoff1, No receive flow control
Transmit Xon1/Xoff1, Receiver compares Xon1/Xoff1
Transmit Xon1/Xoff1, Receiver compares Xon2/Xoff2
Transmit Xon1/Xoff1, Receiver compares Xon1, Xon2/Xoff1, Xoff2
Transmit Xon2/Xoff2, No receive flow control
Transmit Xon2/Xoff2, Receiver compares Xon1/Xoff1
Transmit Xon2/Xoff2, Receiver compares Xon2/Xoff2
Transmit Xon2/Xoff2, Receiver compares Xon1, Xon2/Xoff1, Xoff2
Transmit Xon2/Xoff2, No receive flow control
Transmit Xon2/Xoff2, Xoff2, Receiver compares Xon1/Xoff1
Transmit Xon1, Xon2/Xoff1, Xoff2, Receiver compares Xon2/Xoff2
Transmit Xon1, Xon2/Xoff1, Xoff2, Receiver compares Xon1, Xon2/Xoff1, Xoff2
Rev. 00
11 Page | ||
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