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PDF 25LC020A Data sheet ( Hoja de datos )

Número de pieza 25LC020A
Descripción 2K SPI Bus Serial EEPROM
Fabricantes Microchip Technology 
Logotipo Microchip Technology Logotipo



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25AA020A/25LC020A
2K SPI Bus Serial EEPROM
Device Selection Table
Part Number
VCC Range
25AA020A
25LC020A
1.8-5.5V
2.5-5.5V
Page Size
16 Bytes
16 Bytes
Temp. Ranges
I
I, E
Packages
P, MS, SN, ST, MC, OT
P, MS, SN, ST, MC, OT
Features:
www.DataSheet140U.McoHmz max. clock frequency
• Low-power CMOS technology:
- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 5 μA at 5.5V
• 256 x 8-bit organization
• Write Page mode (up to 16 bytes)
• Sequential Read
• Self-timed Erase and Write cycles (5 ms max.)
• Block Write protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High reliability:
- Endurance: 1,000,000 Erase/Write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature ranges supported:
- Industrial (I):
-40°C to +85°C
- Automotive (E):
-40°C to +125°C
• Pb-Free packages available
Pin Function Table
Name
Function
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
Chip Select Input
Serial Data Output
Write-Protect
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
Description:
The Microchip Technology Inc. 25XX020A* is a 2 Kbit
Serial Electrically Erasable Programmable Read-Only
Memory (EEPROM). The memory is accessed via a
simple Serial Peripheral Interface™ (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25XX020A is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packages including 8-lead MSOP, 8-lead TSSOP and
rotated TSSOP, 8-lead 2x3 DFN, and 6-lead SOT-23.
Package Types (not to scale)
TSSOP/MSOP
(ST, MS)
PDIP/SOIC
(P, SN)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
SOT-23
(OT)
SCK
VSS
SI
1
2
3
6 VDD
5 CS
4 SO
DFN
(MC)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
X-Rotated TSSOP
(X/ST)
HOLD
VCC
CS
SO
1
2
3
4
8 SCK
7 SI
6 VSS
5 WP
*25XX020A is used in this document as a generic part number for the
25AA020A and the 25LC020A.
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 1

1 page




25LC020A pdf
25AA020A/25LC020A
FIGURE 1-1: HOLD TIMING
CS
16
SCK
SO n + 2
n+1
17
18
n
17
16
19
high-impedance
n
SI
n+2
n+1
n
don’t care
5
n
HOLD
www.DataSheet4U.com
n-1
n-1
FIGURE 1-2: SERIAL INPUT TIMING
CS
2
Mode 1,1
SCK Mode 0,0
5
6
SI MSB in
7
4
12
11
83
LSB in
high-impedance
SO
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
9 10
13
MSB out
don’t care
14
3
15
ISB out
Mode 1,1
Mode 0,0
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 5

5 Page





25LC020A arduino
25AA020A/25LC020A
2.6 Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows
the user to write to the nonvolatile bits in the STATUS
register as shown in Table 2-2. See Figure 2-7 for the
WRSR timing sequence. Four levels of protection for
the array are selectable by writing to the appropriate
bits in the STATUS register. The user has the ability to
write-protect none, one, two, or all four of the
segments of the array as shown in Table 2-3.
TABLE 2-3:
BP1
0
0
1
1
ARRAY PROTECTION
BP0
Array Addresses
Write-Protected
0 none
1 upper 1/4
(C0h-FFh)
0 upper 1/2
(80h-FFh)
1 all
(00h-FFh)
FIGURE 2-7:
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
www.DataSheet4CUS.com
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
instruction
data to STATUS register
0 00 00 0 01 7 6 54 3 2 10
high-impedance
SO
Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 11

11 Page







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