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PDF MX29SL800CB Data sheet ( Hoja de datos )
| Número de pieza | MX29SL800CB | |
| Descripción | 8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE 1.8V ONLY FLASH MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MX29SL800CB (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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MX29SL800C T/B
FEATURES
8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE
1.8V ONLY FLASH MEMORY
• Extended single - supply voltage range 1.65V to 2.2V
• 1,048,576 x 8/524,288 x 16 switchable
• Single power supply operation
- 1.8V only operation for read, erase and program
operation
• Fast access time: 90ns
• Low power consumption
- 12mA maximum active current (10MHz)
- 1uA typical standby current
www.Da• taCShoememt4Ua.ncdomregister architecture
- Byte/word Programming (12us/18us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase
• Status Reply
- Data# polling & Toggle bit for detection of program
and erase operation completion
• Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting program or
erase operation completion
• Hardware reset pin (RESET#)
- Hardware method to reset the device to reading array
data
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotected allows code changes
in previously locked sectors
• CFI (Common Flash Interface) compliant
- Flash device parameters stored on the device and
provide the host system to access
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Package type:
- 48-pin TSOP
- 48-ball CSP
- All Pb-free devices are RoHS Compliant
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 10 years data retention
GENERAL DESCRIPTION
The MX29SL800C T/B is a 8-mega bit Flash memory
organized as 1M bytes of 8 bits or 512K words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29SL800C T/B is packaged in 48-pin TSOP and
48-ball CSP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
The standard MX29SL800C T/B offers access time as
fast as 90ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29SL800C T/B has separate chip enable
(CE#) and output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29SL800C T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29SL800C T/B uses a 1.65V~2.2V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
P/N:PM1224
REV. 1.0, APR. 20, 2006
1
1 page  
MX29SL800C T/B
TABLE 2: MX29SL800CB SECTOR ARCHITECTURE
Sector
Sector Size
Byte Mode Word Mode
SA0 16Kbytes 8Kwords
SA1 8Kbytes 4Kwords
SA2 8Kbytes 4Kwords
SA3 32Kbytes 16Kwords
SA4 64Kbytes 32Kwords
www.DaStaASh5eet4U6.c4oKmbytes 32Kwords
SA6 64Kbytes 32Kwords
SA7 64Kbytes 32Kwords
SA8 64Kbytes 32Kwords
SA9 64Kbytes 32Kwords
SA10 64Kbytes 32Kwords
SA11 64Kbytes 32Kwords
SA12 64Kbytes 32Kwords
SA13 64Kbytes 32Kwords
SA14 64Kbytes 32Kwords
SA15 64Kbytes 32Kwords
SA16 64Kbytes 32Kwords
SA17 64Kbytes 32Kwords
SA18 64Kbytes 32Kwords
Address range
Byte Mode (x8) Word Mode (x16)
00000h-03FFFh 00000h-01FFFh
04000h-05FFFh 02000h-02FFFh
06000h-07FFFh 03000h-03FFFh
08000h-0FFFFh 04000h-07FFFh
10000h-1FFFFh 08000h-0FFFFh
20000h-2FFFFh 10000h-17FFFh
30000h-3FFFFh 18000h-1FFFFh
40000h-4FFFFh 20000h-27FFFh
50000h-5FFFFh 28000h-2FFFFh
60000h-6FFFFh 30000h-37FFFh
70000h-7FFFFh 38000h-3FFFFh
80000h-8FFFFh 40000h-47FFFh
90000h-9FFFFh 48000h-4FFFFh
A0000h-AFFFFh 50000h-57FFFh
B0000h-BFFFFh 58000h-5FFFFh
C0000h-CFFFFh 60000h-67FFFh
D0000h-DFFFFh 68000h-6FFFFh
E0000h-EFFFFh 70000h-77FFFh
F0000h-FFFFFh 78000h-7FFFFh
Sector Address
A18 A17 A16 A15 A14 A13 A12
000000 X
000001 0
000001 1
00001X X
0 0 0 1XX X
0 0 1 0XX X
0 0 1 1XX X
0 1 0 0XX X
0 1 0 1XX X
0 1 1 0XX X
0 1 1 1XX X
1 0 0 0XX X
1 0 0 1XX X
1 0 1 0XX X
1 0 1 1XX X
1 1 0 0XX X
1 1 0 1XX X
1 1 1 0XX X
1 1 1 1XX X
Note: Byte mode:address range A18:A-1, word mode:address range A18:A0.
P/N:PM1224
REV. 1.0, APR. 20, 2006
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5 Page 
MX29SL800C T/B
TABLE 5. MX29SL800C T/B COMMAND DEFINITIONS
Command
First Bus
Bus Cycle
Second Bus Third Bus
Cycle
Cycle
Fourth Bus
Cycle
Cycle Addr Data Addr Data Addr Data Addr Data
Fifth Bus
Cycle
Sixth Bus
Cycle
Addr Data Addr Data
Reset
1 XXXH F0H
Read
1 RA RD
Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI
Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI
www.DaStaeSchtoerePt4rUo.tceocmt Word 4 555H AAH 2AAH 55H 555H 90H (SA) XX00H
Verify
x02H XX01H
Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00H
x04H 01H
Program
Word 4 555H AAH 2AAH 55H 555H A0H PA PD
Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD
Chip Erase
Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H
Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H
Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 30H
Sector Erase Suspend 1 XXXH B0H
Sector Erase Resume 1 XXXH 30H
CFI Query
Word 1 55H 98
Byte 1 AAH 98
Sector Protect Word 4 XXXH 60H SPA 60H SPA 40H SPA SD
(Note 6,7)
Byte 4 XXXH 60H SPA 60H SPA 40H SPA SD
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, 22EAH/EAH(Top), and 226BH/6BH(Bottom) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector.
3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or
555H to Address A10~A-1 in byte mode.
Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).
Write Sequence may be initiated with A11~A18 in either state.
4. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,
it means the sector is still not being protected.
5. Any number of CFI data read cycle are permitted.
6. Set sector address (SA) with (A6, A1, A0)=(0,1,0).
7. This command is valid while RESET#=VID.
P/N:PM1224
REV. 1.0, APR. 20, 2006
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX29SL800CB.PDF ] | |
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