PDF IS42S16160B Data sheet ( Hoja de datos )

Número de pieza	IS42S16160B
Descripción	16Meg x16 256-MBIT SYNCHRONOUS DRAM
Fabricantes	Integrated Silicon Solution
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No Preview Available ! IS42S83200B IS42S16160B 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM ISSI® PRELIMINARY INFORMATION MAY 2006 FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge www.D•ataInShteerent4aUl.cboamnk for hiding row access/precharge • Power supply IS42S83200B VDD VDDQ 3.3V 3.3V IS42S16160B 3.3V 3.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • Self Refresh • 8K refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Available in Industrial Temperature • Available in 54-pin TSOP-II and 54-ball BGA (x16 only) • Available in Lead-free OVERVIEW ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. IS42S83200B IS42S16160B 8M x 8 x 4 Banks 4M x16x4 Banks 54-pin TSOPII 54-pin TSOPII 54-ball BGA KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 -7 67 8 10 166 143 125 100 5.4 5.4 6.5 6.5 Unit ns ns Mhz Mhz ns ns Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARYINFORMATION,Rev. 00E 05/25/06 1 1 page IS42S83200B, IS42S16160B ISSI ® PIN CONFIGURATION 54-ball fBGA for x16 (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch) PACKAGE CODE: B 123456789 www.DataSheet4U.com A VSS DQ15 VSSQ B DQ14 DQ13 VDDQ C DQ12 DQ11 VSSQ D DQ10 DQ9 VDDQ E DQ8 NC VSS F DQMH CLK CKE G A12 A11 A9 H A8 A7 A6 J VSS A5 A4 VDDQ DQ0 VDD VSSQ DQ2 DQ1 VDDQ DQ4 DQ3 VSSQ DQ6 DQ5 VDD DQML DQ7 CAS RAS WE BA0 BA1 CS A0 A1 A10 A3 A2 VDD PIN DESCRIPTIONS A0-A12 A0-A8 BA0, BA1 DQ0 to DQ15 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQML DQMH VDD Vss VDDQ VssQ NC Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARYINFORMATION Rev. 00E 05/25/06 Write Enable x16 Lower Byte Input/Output Mask x16 Upper Byte Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection 5 5 Page IS42S83200B, IS42S16160B ISSI ® FUNCTIONAL TRUTH TABLE Continued: Current State Read with auto Precharging www.DataSheet4U.com Write with Auto Precharge Precharging Row Activating CS RAS CAS WE H× × × LH H H LH H L LH L H LH L L LL HH LL HL LL L H LL L L H× ×× LH H H LH H L LH L H LH L L LL HH LL HL LL L H LL L L H× × × LH H H LH H L LH L H LH L L LL HH LL HL LL L H LL L L H× × × LH H H LH H L LH L H LH L L LL HH LL HL LL L H LL L L Address × x × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA Command DESL Action Continue burst to end, Precharge NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Continue burst to end, Precharge ILLEGAL ILLEGAL (11) ILLEGAL (11) ILLEGAL (3) ILLEGAL (11) ILLEGAL ILLEGAL Continue burst to end, Write recovering with auto precharge Continue burst to end, Write recovering with auto precharge ILLEGAL ILLEGAL(11) ILLEGAL (11) ILLEGAL (3,11) ILLEGAL (3,11) ILLEGAL ILLEGAL Nop, Enter idle after tRP Nop, Enter idle after tRP Nop, Enter idle after tRP ILLEGAL (3) ILLEGAL (3) ILLEGAL(3) Nop Enter idle after tRP ILLEGAL ILLEGAL Nop, Enter bank active after tRCD Nop, Enter bank active after tRCD Nop, Enter bank active after tRCD ILLEGAL (3) ILLEGAL (3) ILLEGAL (3,9) ILLEGAL (3) ILLEGAL ILLEGAL Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARYINFORMATION Rev. 00E 05/25/06 11 11 Page

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Número de pieza	Descripción	Fabricantes
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