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PDF H55S2562JFR-60M Data sheet ( Hoja de datos )
| Número de pieza | H55S2562JFR-60M | |
| Descripción | 256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O
Specification of
256M (16Mx16bit) Mobile SDRAM
Memory Cell Array
- Organized as 4banks of 4,194,304 x16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.1 / July. 2009
1
1 page  
11
256Mbit (16Mx16biwtw)wM.DoatbaSihleeeSt4DU.cRom
H55S2562JFR Series
FEATURES
● Standard SDRAM Protocol
● Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
● MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write
for that bank is performed
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
● Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V
● LVCMOS compatible I/O Interface
● Low Voltage interface to reduce I/O power
● Programmable burst length: 1, 2, 4, 8 or full page
● Programmable Burst Type: sequential or interleaved
● Programmable CAS latency of 3 or 2
● Programmable Drive Strength
● Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
● Operating Temperature
- Mobile Temp.: -30oC ~ 85oC
● Package Type
- 54ball FBGA, 0.8mm pitch, 8mm x 8mm, t=1.0mm max
● This product is in compliance with the directive pertaining of RoHS.
Rev 1.1 / July. 2009
5
5 Page 
11
256Mbit (16Mx16biwtw)wM.DoatbaSihleeeSt4DU.cRom
H55S2562JFR Series
DC CHARACTERISTICS II (TA= -30 to 85oC)
Parameter
Symbol
Test Condition
Speed
Unit Note
166MHz 133MHz 105MHz
Operating Current
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
50
40
40 mA 1
Precharge Standby Current IDD2P CKE ≤ VIL(max), tCK = min
in Power Down Mode
IDD2PS CKE ≤ VIL(max), tCK = ∞
0.3 mA
0.3 mA
IDD2N
Precharge Standby Current
in Non Power Down Mode
CKE ≥ VIH(min), CS ≥ VIH(min),
tCK = min, Input signals are
changed one time during 2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
5
1
mA
Active Standby Current
in Power Down Mode
IDD3P CKE ≤ VIL(max), tCK = min
IDD3PS CKE ≤ VIL(max), tCK = ∞
3
mA
3
Active Standby Current
in Non Power Down Mode
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCK = min, Input signals are
changed one time during 2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
10
5
mA
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
55 45 45 mA 1
Auto Refresh Current
IDD5 tRFC ≥ tRFC(min),
70 mA
Self Refresh Current
IDD6 CKE ≤ 0.2V
See Next Page
mA 2
Standby Current in
Deep Power Down Mode
IDD7
See p.50~51
10 uA 3
Note:
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2. See the tables of next page for more specific IDD6 current values.
Rev 1.1 / July. 2009
11
11 Page | ||
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