PDF 48LC8M16A2 Data sheet ( Hoja de datos )

Número de pieza	48LC8M16A2
Descripción	MT48LC8M16A2
Fabricantes	Micron Technology
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No Preview Available ! 128Mbw:wwx.D4a,taxSh8ee,t4xU.1co6m SDRAM SYNCHRONOUS DRAM MT48LC32M4A2 – 8 Meg x 4 x 4 banks MT48LC16M8A2 – 4 Meg x 8 x 4 banks MT48LC8M16A2 – 2 Meg x 16 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/dramds FEATURES • PC100-, and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes • Self Refresh Mode; standard and low power • 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply OPTIONS • Configurations 32 Meg x 4 (8 Meg x 4 x 4 banks) 16 Meg x 8 (4 Meg x 8 x 4 banks) 8 Meg x 16 (2 Meg x 16 x 4 banks) • WRITE Recovery (tWR) tWR = “2 CLK”1 • Package/Pinout Plastic Package – OCPL2 54-pin TSOP II (400 mil) 60-ball FBGA (8mm x 16mm) 60-ball FBGA (11mm x 13mm) • Timing (Cycle Time) 10ns @ CL = 2 (PC100) 7.5ns @ CL = 3 (PC133) 7.5ns @ CL = 2 (PC133) • Self Refresh Standard Low power • Operating Temperature Range Commercial (0oC to +70oC) Industrial (-40oC to +85oC) MARKING 32M4 16M8 8M16 A2 TG FB 3,6 FC 3,6 -8E 3,4,5 -75 -7E None L None IT 3 Part Number Example: MT48LC16M8A2TG-7E NOTE: 1. Refer to Micron Technical Note: TN-48-05. 2. Off-center parting line. 3. Consult Micron for availability. 4. Not recommended for new designs. 5. Shown for PC100 compatability. 6. See page 59 for FBGA Device Marking Table. PIN ASSIGNMENT (Top View) x4 x8 x16 - - VDD NC DQ0 DQ0 - - VDDQ NC NC DQ1 DQ0 DQ1 DQ2 - - VssQ NC NC DQ3 NC DQ2 DQ4 - - VDDQ NC NC DQ5 DQ1 DQ3 DQ6 - - VssQ NC NC DQ7 - - VDD NC NC DQML - - WE# - - CAS# - - RAS# - - CS# - - BA0 - - BA1 - - A10 - - A0 - - A1 - - A2 - - A3 - - VDD 54-Pin TSOP 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 9 46 10 45 11 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 x16 x8 x4 Vss - - DQ15 DQ7 NC VssQ - - DQ14 NC NC DQ13 DQ6 DQ3 VDDQ - - DQ12 NC NC DQ11 DQ5 NC VssQ - - DQ10 NC NC DQ9 DQ4 DQ2 VDDQ - - DQ8 NC NC Vss - - NC - - DQMH DQM DQM CLK - - CKE - - NC - - A11 - - A9 - - A8 - - A7 - - A6 - - A5 - - A4 - - Vss - - Note: The # symbol indicates signal is active LOW. A dash (–) indicates x8 and x4 pin function is same as x16 pin function. 32 Meg x 4 16 Meg x 8 8 Meg x 16 Configuration 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks Refresh Count 4K 4K 4K Row Addressing 4K (A0–A11) 4K (A0–A11) 4K (A0–A11) Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Column Addressing 2K (A0–A9, A11) 1K (A0–A9) 512 (A0–A8) KEY TIMING PARAMETERS SPEED CLOCK ACCESS TIME SETUP GRADE FREQUENCY CL = 2* CL = 3* TIME -7E 143 MHz – 5.4ns 1.5ns -7E 133 MHz 5.4ns – 1.5ns -75 -8E 3,4,5 -75 -8E 3 ,4,5 133 MHz 125 MHz 100 MHz 100 MHz – 5.4ns 1.5ns – 6ns 2ns 6ns – 1.5ns 6ns – 2ns HOLD TIME 0.8ns 0.8ns 0.8ns 1ns 0.8ns 1ns *CL = CAS (READ) latency 128Mb: x4, x8, x16 SDRAM 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 1 page 128Mbw:wwx.D4a,taxSh8ee,t4xU.1co6m SDRAM FUNCTIONAL BLOCK DIAGRAM 32 Meg x 4 SDRAM CKE CLK CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER 12 A0-A11, BA0, BA1 14 ADDRESS REGISTER REFRESH 12 COUNTER 12 ROW- ADDRESS MUX 12 BANK0 ROW- ADDRESS LATCH & DECODER 4096 BANK0 MEMORY ARRAY (4,096 x 2,048 x 4) SENSE AMPLIFIERS 4096 2 BANK CONTROL LOGIC 2 COLUMN- ADDRESS 11 11 COUNTER/ LATCH I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2048 (x4) COLUMN DECODER 11 DATA 4 OUTPUT REGISTER DATA 4 INPUT REGISTER 4 DQM DQ0- DQ3 128Mb: x4, x8, x16 SDRAM 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 5 Page CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequen- cies at which each CAS latency setting can be used. Reserved states should not be used as unknown op- eration or incompatibility with future versions may result. CLK COMMAND DQ T0 T1 T2 READ NOP tLZ tAC CAS Latency = 2 NOP tOH DOUT T3 128Mbw:wwx.D4a,taxSh8ee,t4xU.1co6m SDRAM Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with fu- ture versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. SPEED -7E -75 -8E Table 2 CAS Latency ALLOWABLE OPERATING FREQUENCY (MHz) CAS LATENCY = 2 CAS LATENCY = 3 ≤ 133 ≤ 100 ≤ 100 ≤ 143 ≤ 133 ≤ 125 CLK COMMAND T0 READ DQ T1 T2 NOP NOP tLZ tAC CAS Latency = 3 Figure 2 CAS Latency T3 T4 NOP tOH DOUT DON’T CARE UNDEFINED 128Mb: x4, x8, x16 SDRAM 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc. 11 Page

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