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PDF STE2001 Data sheet ( Hoja de datos )
| Número de pieza | STE2001 | |
| Descripción | 65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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www.DataSheet4U.com
STE2001
65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
PRODUCT PREVIEW
s 65 x 128 bits Display Data RAM
s Configurable matrix: 65 x 128 or 33 x 128
s Programmable (65/33) MUX rate
s Row by Row Scrolling
s Automatic data RAM Blanking procedure
s Selectable Input Interface:
• I2C Bus Fast and Hs-mode (read and write)
• Parallel Interface (write only)
• Serial Interface (write only)
s Fully Integrated Oscillator requires no external
components
s Fully Integrated Configurable LCD bias voltages
generator with:
• Selectable (5X, 4X, 3X, 2X) multiplication factor
• Effective sensing for High Precision Output
• Four selectable temperature compensation
coefficients
s Designed for chip-on-glass (COG) applications
s Programmable bottom row pads mirroring and
top row pads mirroring for compatible with both
TCP and COG applications
s Low Power Consumption, suitable for battery
operated systems
s Logic Supply Voltage range from 1.9 to 5V
s High Voltage Generator Supply Voltage range
from 2.4 to 4.5V
s Display Supply Voltage range from 4.5 to 9V
DESCRIPTION
The STE2001 is a low power CMOS LCD controller
driver. Designed to drive a 65 rows by 128 columns
graphic display, provides all necessary functions in a
single chip, including on-chip LCD supply and bias
voltages generators, resulting in a minimum of exter-
nals components and in a very low power consump-
tion. The STE2001 features three standard interfaces
(Serial, parallel, I2C) for ease of interfacing with the
host µcontroller.
Type
Ordering Number
Bumped Wafers
STE2001DIE1
Bumped Dice on Waffle Pack
STE2001DIE2
Figure 1. Block Diagram
CO to C127
R0 to R64
OSC
VLCDIN
VLCDSENSE
VLCDOUT
RES
VDD1,2,3
VSS1,2
SEL1,2
OSC
TIMING
GENERATOR
COLUMN
DRIVERS
BIAS VOLTAGE
GENERATOR
CLOCK
DATA
LATCHES
HIGH VOLTAGE
GENERATOR
RESET
65 x 128
RAM
ROW
DRIVERS
SHIFT
REGISTER
SCROLL
LOGIC
DATA
REGISTER
INSTRUCTION
REGISTER
DISPLAY
CONTROL
LOGIC
TEST
TEST_0_13
BSY_FLG
I2CBUS
PARALLEL
SERIAL
SAO SCL SDA_IN SDA_OUT DB0 to DB7 E PD/C SCE SDIN SCLK SD/C D00IN1137
October 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
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STE2001
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
FFRAME Frame frequency
fosc or fext = 38 kHz; note 1
TVHRL Vdd1 to RES Low
note 2 and 10; CVLCD = 1µF
Tw(RES) RES LOW pulse width
Reset Pulse Rejection
note 3
Tamb = 25°C; note 11
Reset Pulse Rejection
note 11
TSTART Reset Pulse vs. Device Ready
TVDD
I2C BUS INTERFACE (See note 4)
FSCL SCL Clock Frequency
Fast Mode ; VDD1 =4.5V
VDD1 =18V; Tamb = -20 to 70°C
High Speed Mode; Cb=100pF
(max); note 6; VDD1 =4.5V
High Speed Mode; Cb=400pF
(max); note 6 ; VDD1 =4.5V
TSCLL Cb=100pF
TSCLH Cb=100pF
TSCLL Cb=400pF
TSCLH Cb=400pF
TSU;DAT Cb=100pF
THD;DAT Cb=100pF
TSU;DAT Cb=400pF
THD;DAT Cb=400pF
TSU;STA Cb=100pF
Note 8
TSU;STA Cb=400pF
Note 8
THD;STA Cb=100pF
Note 8
THD;STA Cb=400pF
Note 8
TSU;STO Cb=100pF
Note 8
TSU;STO Cb=400pF
Note 8
TrCL Cb=100pF
Note 5, 8
TrCL Cb=400pF
Note 5, 8
TrCL1 Cb=100pF
Note 5, 8
TrCL1 Cb=400pF
Note 5, 8
TrDA
TrDA
Cb=100pF
Cb=400pF
Note 5, 8
Note 5, 8
TfCL Cb=100pF
Note 5, 8
TfCL Cb=400pF
Note 5, 8
Min.
0
600
1
0
DC
DC
DC
160
160
320
320
Typ.
73
370
3.4
30
30
30
30
170
330
170
330
170
330
25
50
30
120
30
120
25
50
Max.
5
200
400
400
1.7
Unit
Hz
ms
ns
µs
µs
ms
kHz
kHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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STE2001
Figure 11. Output drivers rows and logical memory rows correspondence with MY = 0
ROW DRIVER MUX 33 PHYSICAL MEMORY ROW
R16
to
R23
Row 0
to
Row 7
01234567
120 121 122 123 124 125 126 127
BANK 4
R24 Row 8
to to
R31 Row15
BANK 5
R48 Row 16
to to
R55 Row 23
BANK 6
R56 Row 24
to to
R63 Row 31
BANK 7
R64 Row 32
BANK 8
D00IN1148
Figure 12. Output drivers rows and logical memory rows correspondence with MY = 1
ROW DRIVER MUX 33 PHYSICAL MEMORY ROW
01234567
120 121 122 123 124 125 126 127
R16 Row 0
to to
R23 Row 7
BANK 4
R24 Row 8
to to
R31 Row15
BANK 5
R48 Row 16
to to
R55 Row 23
BANK 6
R56 Row 24
to to
R63 Row 31
BANK 7
R64 Row 32
BANK 8
D00IN1148
Instruction Set
Two different instructions formats are provided:
- With D/C set to LOW
commands are sent to the Control circuitry.
- With D/C set to HIGH
the Data RAM is addressed Instructions have the syntax summarized in Table.1.
Reset (RES)
At power-on, all internal registers and RAM content are not defined. A Reset pulse must be applied on RES pad
(active low) to initialize the internal registers content (see Tables 3,4,5,&6). Every on-going communication with
the host controller is interrupted. The IC after the reset pulse is programmed in Power Down mode.
The Default configurations is:
- Horizontal addressing (V = 0)
- Normal instruction set (H = 0)
- Normal display (MX = MY = TRS =BRS = 0)
- MUX 65 mode (MUX = 0)
11/36
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| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet STE2001.PDF ] | |
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