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IS61LF6432A の電気的特性と機能

IS61LF6432AのメーカーはIntegrated Silicon Solutionです、この部品の機能は「SYNCHRONOUS FLOW-THROUGH STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61LF6432A
部品説明 SYNCHRONOUS FLOW-THROUGH STATIC RAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS61LF6432A Datasheet, IS61LF6432A PDF,ピン配置, 機能
IS61LF6436A
IS61LF6432A
64K x 32, 64Kx36
SYNCHRONOUS FLOW-THROUGH
STATIC RAM
ISSI®
www.DataSheet4U.com
OCTOBER 2005
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP package
• Power Supply:
+3.3V VDD
+3.3V or 2.5V VDDQ
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
• Industrial Temperature Available:
(-40oC to +85oC)
• Lead-free available
DESCRIPTION
The ISSI IS61LF6432A and IS61LF6436A are high-speed,
low-power synchronous static RAM designed to provide a
burstable, high-performance, memory. IS61LF6432A is
organized as 65,536 words by 32 bits. IS61LF6436A is
organized as 65,536 words by 36 bits. They are fabricated
with ISSI's advanced CMOS technology. The device inte-
grates a 2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BWa controls DQa, BWb controls DQb, BWc controls DQc,
BWd controls DQd, conditioned by BWE being LOW. A
LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61LF6432A/36A and controlled by the
ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW. Inter-
leave burst is achieved when this pin is tied HIGH or left
floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
8.5
8.5
11
90
Unit
ns
ns
MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
1

1 Page





IS61LF6432A pdf, ピン配列
IS61LF6436A
IS61LF6432A
PIN CONFIGURATION
100-Pin TQFP
NC
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
NC
VDD
NC
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
NC
ISSI®
www.DataSheet4U.com
64K x 32
PIN DESCRIPTIONS
A0, A1
A
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VDD +3.3V Power Supply
Vss Ground
VDDQ
Isolated Output Buffer Supply: +3.3V
or 2.5V
ZZ Snooze Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
3


3Pages


IS61LF6432A 電子部品, 半導体
IS61LF6436A
IS61LF6432A
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
ISSI®
www.DataSheet4U.com
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
A1', A0' = 1,1
0,0
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
TSTG
Storage Temperature
PD Power Dissipation
IOUT Output Current (per I/O)
VIN, VOUT Voltage Relative to Vss for I/O Pins
VIN Voltage Relative to Vss for
for Address and Control Inputs
VDD Voltage on VDD Supply Relative to Vss
Value
–55 to +150
1.6
100
–0.5 to VDDQ + 0.3
–0.5 to VDD + 0.5
Unit
°C
W
mA
V
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05

6 Page



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部品番号部品説明メーカ
IS61LF6432A

SYNCHRONOUS FLOW-THROUGH STATIC RAM

Integrated Silicon Solution
Integrated Silicon Solution


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