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PDF IS45S16400F Data sheet ( Hoja de datos )
| Número de pieza | IS45S16400F | |
| Descripción | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM | |
| Fabricantes | Integrated Silicon Solution | |
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IS42S16400F
IS45S16400F
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
www.DataSheet4U.com
NOVEMBER 2009
FEATURES
• Clock frequency: 200, 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• Auto refresh (CBR)
• 4096 refresh cycles every 64 ms (Com, Ind, A1
grade) or 16ms (A2 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
54-pin TSOP II
54-ball FBGA (8mm x 8mm)
• Operating Temperature Range
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade A1 (-40oC to +85oC)
Automotive Grade A2 (-40oC to +105oC)
OVERVIEW
ISSI's 64Mb Synchronous DRAM is organized as 1,048,576
bits x 16-bit x 4-bank for improved performance. The
synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-5 -6
5 6
7.5 7.5
200 166
133 133
5 5.4
6 6
-7 Unit
7 ns
7.5 ns
143 Mhz
133 Mhz
5.4 ns
6 ns
ADDRESS TABLE
Parameter
4M x 16
Configuration
1M x 16 x 4
banks
Refresh Count
Com./Ind.
A1
A2
4K/64ms
4K/64ms
4K/16ms
Row Addresses
A0-A11
Column Addresses
A0-A7
Bank Address Pins
BA0, BA1
Auto Precharge Pins
A10/AP
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
11/09/09
1
1 page  
IS42S16400F
IS45S16400F
www.DataSheet4U.com
PIN FUNCTIONS
Symbol TSOP Pin No.
Type
A0-A11
23 to 26
Input Pin
29 to 34
22, 35
BA0, BA1
CAS
CKE
20, 21
17
37
Input Pin
Input Pin
Input Pin
CLK 38 Input Pin
CS
19 Input Pin
DQ0 to
DQ15
LDQM,
UDQM
2, 4, 5, 7, 8, 10,
11,13, 42, 44, 45,
47, 48, 50, 51, 53
15, 39
DQ Pin
Input Pin
RAS
WE
Vddq
Vdd
GNDq
GND
18 Input Pin
16 Input Pin
3, 9, 43, 49
1, 14, 27
6, 12, 46, 52
28, 41, 54
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQ0 to DQ15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs
go to the HIGH impedance state when LDQM/UDQM is HIGH. This function cor-
responds to OE in conventional DRAMs. In write mode, LDQM and UDQM control
the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is en-
abled, and data can be written to the device. When LDQM or UDQM is HIGH, input
data is masked and cannot be written to the device.
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
Vddq is the output buffer power supply.
Vdd is the device internal power supply.
GNDq is the output buffer ground.
GND is the device internal ground.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
11/09/09
5
5 Page 
IS42S16400F
IS45S16400F
www.DataSheet4U.com
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m (1-6)
CURRENT STATE COMMAND (ACTION)
Any
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Idle Any Command Otherwise Allowed to Bank m
Row
ACTIVE (Select and activate row)
Activating,
READ (Select column and start READ burst)(7)
Active, or
WRITE (Select column and start WRITE burst)(7)
Precharging
PRECHARGE
Read
ACTIVE (Select and activate row)
(Auto
READ (Select column and start new READ burst)(7,10)
Precharge
WRITE (Select column and start WRITE burst)(7,11)
Disabled)
PRECHARGE(9)
Write
ACTIVE (Select and activate row)
(Auto
READ (Select column and start READ burst)(7,12)
Precharge
WRITE (Select column and start new WRITE burst)(7,13)
Disabled)
PRECHARGE(9)
Read
ACTIVE (Select and activate row)
(With Auto
READ (Select column and start new READ burst)(7,8,14)
Precharge)
WRITE (Select column and start WRITE burst)(7,8,15)
PRECHARGE(9)
Write
ACTIVE (Select and activate row)
(With Auto
READ (Select column and start READ burst)(7,8,16)
Precharge)
WRITE (Select column and start new WRITE burst)(7,8,17)
PRECHARGE(9)
CS RAS CAS WE
H X X X
L H H H
X X X X
L L H H
L H L H
L H L L
L L H L
L L H H
L H L H
L H L L
L L H L
L L H H
L H L H
L H L L
L L H L
L L H H
L H L H
L H L L
L L H L
L L H H
L H L H
L H L L
L L H L
NOTE:
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (Truth Table - CKE) and after txsr has been met (if the previ-
ous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Excep-
tions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and trp has been met.
Row Active: A row in the bank has been activated, and trcd has been met. No data bursts/accesses and no register
accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when trp has been
met. Once trp is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when trp has been
met. Once trp is met, the bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
11/09/09
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS45S16400F.PDF ] | |
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