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PDF IS45S16400C1 Data sheet ( Hoja de datos )
| Número de pieza | IS45S16400C1 | |
| Descripción | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM | |
| Fabricantes | Integrated Silicon Solution | |
| Logotipo |  |
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IS45S16400C1
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
ISSI®
www.DataSheet4U.com
OCTOBER 2005
FEATURES
• Clock frequency: 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Automotive Temperature Range
Option A: 0oC to +70oC
Option A1: -40oC to +85oC
• Package: 400-mil 54-pin TSOP II
• Lead-free package is available
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS45S16400C1 is
organized as 1,048,576 bits x 16-bit x 4-bank for improved
performance. ThesynchronousDRAMsachievehigh-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
VDD
DQ0
VDDQ
DQ1
DQ2
GNDQ
DQ3
DQ4
VDDQ
DQ5
DQ6
GNDQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 GND
53 DQ15
52 GNDQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 GNDQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 GND
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 GND
PIN DESCRIPTIONS
A0-A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM
UDQM
VDD
GND
VDDQ
GNDQ
NC
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
10/25/05
1
1 page  
IS45S16400C1
enabled or disabled. AUTO PRECHARGE does not apply
except in full-page burst mode. Upon completion of the
READ or WRITE burst, a precharge of the bank/row that
is addressed is automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (tRC)
is required for a single refresh operation, and no other
commands can be executed during this period. This com-
mand is executed at least 4096 times every 64ms. During
an AUTO REFRESH command, address bits are “Don’t
Care”. This command corresponds to CBR Auto-refresh.
SELF REFRESH
During the SELF REFRESH operation, the row address to
be refreshed, the bank, and the refresh interval are
generated automatically internally. SELF REFRESH can
be used to retain data in the SDRAM without external
clocking, even if the rest of the system is powered down.
The SELF REFRESH operation is started by dropping the
CKE pin from HIGH to LOW. During the SELF REFRESH
operation all other inputs to the SDRAM become “Don’t
Care”. The device must remain in self refresh mode for a
minimum period equal to tRAS or may remain in self refresh
mode for an indefinite period beyond that. The SELF-
REFRESH operation continues as long as the CKE pin
remains LOW and there is no need for external control of
any other pins. The next command cannot be executed until
the device internal recovery period (tRC) has elapsed. Once
CKE goes HIGH, the NOP command must be issued
(minimum of two clocks) to provide time for the completion of
any internal refresh in progress. After the self-refresh, since
it is impossible to determine the address of the last row to
be refreshed, an AUTO-REFRESH should immediately be
performed for all addresses.
ISSI ®
www.DataSheet4U.com
BURST TERMINATE
The BURST TERMINATE command forcibly terminates the
burst read and write operations by truncating either fixed-
length or full-page bursts and the most recently registered
READ or WRITE command prior to the BURST TERMI-
NATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open for
accesses.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
10/25/05
5
5 Page 
IS45S16400C1
ISSI ®
www.DataSheet4U.com
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VDD MAX
VDDQ MAX
VIN
VOUT
PD MAX
ICS
TOPR
TSTG
Parameters
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage
Output Voltage
Allowable Power Dissipation
Output Shorted Current
Operating Temperature
A
A1
Storage Temperature
Rating
–0.5 to +4.6
–0.5 to +4.6
–0.5 to VDDQ + 0.5
–1.0 to VDDQ + 0.5
1
50
0 to +70
–40 to +85
–65 to +150
Unit
V
V
V
V
W
mA
°C
°C
DC RECOMMENDED OPERATING CONDITIONS(2)
(A: At TA = 0°C to +70°C, A1: At TA = -40°C to +85°C)
Symbol
VDD, VDDQ
VIH
VIL
Parameter
Supply Voltage
Input High Voltage(3)
Input Low Voltage(4)
Min.
3.0
2.0
-0.3
Typ.
3.3
—
—
Max.
3.6
VDD + 0.3
+0.8
Unit
V
V
V
CAPACITANCE CHARACTERISTICS(1,2) (At TA = 0 to +25°C, VDD = VDDQ = 3.3 ± 0.3V, f = 1 MHz)
Symbol Parameter
Typ. Max. Unit
CIN
CCLK
CI/O
Input Capacitance: Address and Control
Input Capacitance: (CLK)
Data Input/Output Capacitance: I/O0-I/O15
— 3.8 pF
— 3.5 pF
— 6.5 pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. All voltages are referenced to GND.
3. VIH(max) = VDDQ + 2.0V with a pulse width < 3ns.
4. VIL(min) = GND - 2.0V with a pulse width < 3ns.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
10/25/05
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS45S16400C1.PDF ] | |
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