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IS45S83200D の電気的特性と機能

IS45S83200DのメーカーはIntegrated Silicon Solutionです、この部品の機能は「256-MBIT SYNCHRONOUS DRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS45S83200D
部品説明 256-MBIT SYNCHRONOUS DRAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS45S83200D Datasheet, IS45S83200D PDF,ピン配置, 機能
IS42S83200D, IS42S16160D
IS45S83200D, IS45S16160D
www.DataSheet4U.com
32Meg x 8, 16Meg x16 JUNE 2009
256-MBIT SYNCHRONOUS DRAM
FEATURES
• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single Power supply: 3.3V + 0.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 8K refresh cycles every 16 ms (A2 grade) or
64 ms (commercial, industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
54-pin TSOP-II (x8 and x16)
54-ball BGA (x16 only)
• Operating Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade A1 (-40oC to +85oC)
Automotive Grade A2 (-40oC to +105oC)
• Die Revision: D
OVERVIEW
ISSI's 256Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 256Mb SDRAM is organized as follows.
IS42S83200D IS42S16160D
8M x 8 x 4 Banks 4M x16x4 Banks
54-pin TSOPII 54-pin TSOPII
54-ball BGA (contact Marketing)
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-6 -7
6 7
10 10
166 143
100 100
5.4 5.4
6.5 6.5
-75E Unit
— ns
7.5 ns
— Mhz
133 Mhz
— ns
5.5 ns
ADDRESS TABLE
Parameter
32M x 8
Configuration
8M x 8 x 4
banks
Refresh Count
Com./Ind.
A1
A2
8K/64ms
8K/64ms
8K/16ms
Row Addresses
A0-A12
Column Addresses
A0-A9
Bank Address Pins
BA0, BA1
Auto Precharge Pins
A10/AP
16M x 16
4M x 16 x 4
banks
8K/64ms
8K/64ms
8K/16ms
A0-A12
A0-A8
BA0, BA1
A10/AP
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  B
06/11/09
1

1 Page





IS45S83200D pdf, ピン配列
IS42S83200D, IS42S16160D
IS45S83200D, IS45S16160D
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
www.DataSheet4U.com
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 DQ7
52 VSSQ
51 NC
50 DQ6
49 VDDQ
48 NC
47 DQ5
46 VSSQ
45 NC
44 DQ4
43 VDDQ
42 NC
41 VSS
40 NC
39 DQM
38 CLK
37 CKE
36 A12
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
PIN DESCRIPTIONS
A0-A12
Row Address Input
A0-A9
Column Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ7 Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
WE
DQM
Vdd
Vss
Vddq
Vssq
NC
Write Enable
Data Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  B
06/11/09
3


3Pages


IS45S83200D 電子部品, 半導体
IS42S83200D, IS42S16160D
IS45S83200D, IS45S16160D
PIN FUNCTIONS
Symbol Type
A0-A12
Input Pin
BA0, BA1
CAS
CKE
CLK
CS
DQML,
DQMH
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
DQM
Input Pin
DQ0-DQ7 or
Input/Output
DQ0-DQ15
RAS
Input Pin
WE
Vddq
Vdd
Vssq
Vss
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
www.DataSheet4U.com
Function (In Detail)
Address Inputs: A0-A12 are sampled during the ACTIVE command (row-address
A0-A12) and READ/WRITE command (column address A0-A9 (x8), or A0-A8 (x16);
with A10 defining auto precharge) to select one location out of the memory array in
the respective bank. A10 is sampled during a PRECHARGE command to determine
if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW).
The address inputs also provide the op-code during a LOAD MODE REGISTER
command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to
the HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to
OE in conventional DRAMs. In write mode,DQML and DQMH control the input buffer.
When DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data
can be written to the device. WhenDQML or DQMH is HIGH, input data is masked
and cannot be written to the device. For IS42S16160D only.
For IS42S83200D only.
Data on the Data Bus is latched on DQ pins during Write commands, and buffered for
output after Read commands.
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
Vddq is the output buffer power supply.
Vdd is the device internal power supply.
Vssq is the output buffer ground.
Vss is the device internal ground.
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  B
06/11/09

6 Page



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共有リンク

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