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PDF IS45S83200C Data sheet ( Hoja de datos )

Número de pieza IS45S83200C
Descripción 256 Mb Single Data Rate Synchronous DRAM
Fabricantes Integrated Silicon Solution 
Logotipo Integrated Silicon Solution Logotipo



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IS45S83200C
IS45S16160C
256 Mb Single Data Rate Synchronous DRAM
www.DataSheet4U.com
APRIL 2009
General Description
IS45S83200C is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and
IS45S16160C is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to
the rising edge of CLK. IS45S83200C and IS45S16160C achieve very high speed data rates up to 166MHz, and
are suitable for main memories or graphic memories in computer systems.
Features
- Single 3.3V ±0.3V power supply
- Max. Clock frequency :
- 6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- LDQM and UDQM (IS45S16160C)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 8192 refresh cycles /64ms
- LVTTL Interface
- Package
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
Pb-free package is available
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
04/02/09
1

1 page




IS45S83200C pdf
IS45S83200C
IS45S16160C
www.DataSheet4U.com
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN,VOUT
VDD, VDDQ
TSTG
PD
IOS
Value
-0.5 ~ 4.6
-0.5 ~ 4.6
-65 ~ +150
1.0
50
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, Automotive grade: TA = -40 to 85 oC)
Parameter
Symbol
Min Typ
Max
Supply voltage
Vdd
VddQ
3.0 3.3
3.0 3.3
3.6
3.6
Input logic high voltage
VIH 2.0
VDDQ + 0.3
Input logic low voltage
VIL -0.3 0 0.8
Output logic high voltage
VOH 2.4 -
-
Output logic low voltage
VOL - - 0.4
Input leakage current
ILI
-5 -
5
Output leakage current
IoL -5 - 5
Unit
V
V
V
V
V
V
uA
uA
Note:
1. VIH(max) = VDDQ + 2V AC for pulse width 3ns acceptable.
2. VIL(min) = -2V AC for pulse width 3ns acceptable.
3. Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled , 0V VOUT VDD.
CAPACITANCE ( Vdd =3.3V, TA = 25°C, f = 1MHz
Parameter
Symbol
Clock
Cclk
/CAS,/RAS,/W E,/CS,CK E,L/UDQM
Cin
Address
CADD
DQ0~DQ15
COUT
Min Max Unit
2.5 4.0 pF
2.5 5.0 pF
2.5 5.0 pF
4.0 6.5 pF
Unit
V
V
C
W
mA
Note
1
2
IOH = -0.1mA
IOL = 0.1mA
3
3
Note
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
04/02/09
5

5 Page





IS45S83200C arduino
IS45S83200C
IS45S16160C
www.DataSheet4U.com
Function Truth Table
Current state /CS /RAS
Idle H X
LH
LH
LH
LH
LL
LL
LL
LL
LL
Row active
HX
LH
LH
LH
LH
LL
LL
LL
LL
Read
HX
LH
LH
LH
LH
LL
LL
LL
LL
Write
HX
LH
LH
LH
LH
LL
LL
LL
LL
Read with auto H
precharge
L
X
H
LH
LH
LH
LL
LL
LL
LL
Write with auto H
precharge
L
X
H
LH
LH
LH
LL
LL
LL
LL
/CAS
X
H
H
L
L
H
H
L
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
/WE
X
H
L
H
L
H
L
H
L
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
/Address
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
OC,BA1=H
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
X
X
X
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
OC,BA1=L
Command
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS
EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
DESL
NOP
BST
RD/RDA
WR/WRA
ACT
PRE/PALL
REF
MRS / EMRS
Action
NOP
NOP
NOP
ILLEGAL
ILLEGAL
Row activating
NOP
Auto refresh
Mode register set
Extended mode register set
NOP
NOP
NOP
Begin read
Begin write
ILLEGAL
Precharge / Precharge all banks
ILLEGAL
ILLEGAL
Continue burst to end Row active
Continue burst to end Row active
Burst stop Row active
Terminate burst,begin new read
Terminate burst,begin write
ILLEGAL
Terminate burst Precharging
ILLEGAL
ILLEGAL
Continue burst to end Write recovering
Continue burst to end Write recovering
Burst stop Row active
Terminate burst, start read : Determine AP
Terminate burst,new write : Determine AP
ILLEGAL
Terminate burst Precharging
ILLEGAL
ILLEGAL
Continue burst to end Precharging
Continue burst to end Precharging
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Continue burst to end Write recovering
Continue burst to end Write recovering
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Notes
1
1
2
2
1
3
4
4,5
1
4,5
4
1
6
1
1
1
1
1
1
1
1
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
04/02/09
11

11 Page







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