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PDF AD5535 Data sheet ( Hoja de datos )
| Número de pieza | AD5535 | |
| Descripción | 14-Bit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
32-Channel, 14-Bit DAC with Fuwwllw-.DSactaaShleeet4OU.cuotmput
Voltage Programmable from 50 V to 200 V
AD5535
FEATURES
High integration: 32-channel, 14-bit DAC with integrated,
high voltage output amplifier
Guaranteed monotonic
Housed in 15 × 15 mm CSP-BGA package
Full-scale output voltage programmable from 50 V to 200 V
via reference input
700 µA drive capability
Integrated silicon diode for temperature monitoring
DSP-/microcontroller-compatible serial interface
Channel update rate: 1.2 MHz
Asynchronous RESET facility
Temperature range: –10°C to +85°C
APPLICATIONS
GENERAL DESCRIPTION
The AD5535 is a 32-channel, 14-bit DAC with an on-chip high
voltage output amplifier. This device is targeted for optical
micro-electromechanical systems. The output voltage range is
programmable via the REFIN pin. Output range is 0 V to 50 V
with REFIN = 1 V and is 0 V to 200 V with REFIN = 4 V. Each
amplifier can source 700 µA, which is ideal for the deflection
and control of optical MEMS mirrors.
The selected DAC register is written to via the 3-wire interface.
The serial interface operates at clock rates of up to 30 MHz and
is compatible with DSP and microcontroller interface standards.
The device is operated with AVCC = 4.75 to 5.25 V, DVCC = 2.7 V
to 5.25 V, V– = −4.75 V to −5.25 V, V+ = +4.75 V to +5.25 V, VPP
= 210 V. REF_IN is buffered internally on the AD5535 and
should be driven from a stable reference source.
Optical micro-electromechanical systems (MEMS)
Optical cross-point switches
Micropositioning applications using Piezo Flextures
Level setting in automotive test and measurement
FUNCTIONAL BLOCK DIAGRAM
DVCC
AVCC
REF_IN
VPP PGND
V–
V+
RESET
AD5535
DAC_GND
14-BIT BUS
DAC
DAC
ANODE
CATHODE
R1 VOUT0
RF
R1 VOUT1
RF
AGND
DGND
INTERFACE
CONTROL
LOGIC
DAC
DAC
R1 VOUT30
RF
R1 VOUT31
RF
SCLK DIN SYNC
Figure 1.
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
AD5535www.DataSheet4U.com
TIMING CHARACTERISTICS
VPP = 210 V, V− = –5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V.
All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1, 2, 3
fUPDATE
fCLKIN
t1
t2
t3
t4
t5
t6
t7
t8
t9
A Grade
1.2
30
13
13
15
50
10
10
5
200
20
Unit
MHz max
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
Channel Update Rate
SCLK Frequency
SCLK High Pulse Width
SCLK Low Pulse Width
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
SYNC High Time
DIN Setup Time
DIN Hold Time
19th SCLK Falling Edge to SYNC Falling Edge for Next Write
RESET Pulse Width
1 See timing diagrams in Figure 2.
2 Guaranteed by design and characterization, not production tested.
3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
SCLK
SYNC
DIN
1
t3
t5
t1
2
t2
3
t4
MSB
45
t6
t7
16 17 18 19
t8
LSB
RESET
t9
Figure 2. Serial Interface Timing Diagram
1
Rev. PrE | Page 5 of 16
5 Page 
Preliminary Technical Data
FUNCTIONAL DESCRIPTION
The AD5535 consists of 32 14-bit DACs with 200 V high voltage
amplifiers in a single 15 mm × 15 mm CSP-BGA package. The
output voltage range is programmable via the REFIN pin.
Output range is 0 V to 50 V with REFIN = 1 V, and 0 V to 200 V
with REFIN = 4 V. Communication to the device is through a
serial interface operating at clock rates of up to 30 MHz and is
compatible with DSP and microcontroller interface standards. A
5-bit address and a 14-bit data-word are loaded into the
AD5535 input register via the serial interface. The channel
address is decoded, and the data-word is converted into an
analog output voltage for this channel.
At power-on, all the DAC registers are loaded with 0s.
DIGITAL-TO-ANALOG SECTION
The architecture of each DAC channel consists of a resistor
string DAC followed by an output buffer amplifier operating
with a nominal gain of 50. The voltage at the REF_IN pin
provides the reference voltage for the corresponding DAC. The
input coding to the DAC is straight binary and the ideal DAC
output voltage is given by
VOUT
=
50 ×VREF _ IN
214
×D
where D is the decimal equivalent of the binary code, which is
loaded to the DAC register (0 to 16,383).
The output buffer amplifier is specified to drive a load of 1 MΩ
and 200 pF. The linear output voltage range for the output
amplifier is from 7 V to VPP − 10V. The amplifier output band-
width is typically 5 kHz, and is capable of sourcing 700 µA and
sinking 2.8mA. Settling time for a full-scale step is typically
30 µs with no load and 110 µs with a 200 pF load.
RESET FUNCTION
The reset function on the AD5535 can be used to reset all nodes
on the device to their power-on reset condition. All the DACs
are loaded with 0s and all registers are cleared. The reset
function is implemented by taking the RESET pin low.
SERIAL INTERFACE
The serial interface is controlled by three pins:
• SYNC is the frame synchronization pin for the serial
interface.
• SCLK is the serial clock input. This pin operates at clock
speeds of up to 30 MHz.
• DIN is the serial data input. Data must be valid on the falling
edge of SCLK.
To update a single DAC channel, a 19-bit data-word is written
to the AD5535 input register.
AD5535www.DataSheet4U.com
A4 to A0 Bits
These bits can address any one of the 32 channels. A4 is the
MSB of the address; A0 is the LSB.
DB13 to DB0 Bits
These bits are used to write a 14-bit word into the addressed
DAC register.
Figure 2 is the timing diagram for a serial write to the AD5535.
The serial interface works with both a continuous and a discon-
tinuous serial clock. The first falling edge of SYNC resets a
counter that counts the number of serial clocks to ensure that
the correct number of bits are shifted into the serial shift
register. Any further edges on SYNC are ignored until the
correct number of bits are shifted in. Once 19 bits have been
shifted in, the SCLK is ignored. For another serial transfer to
take place, the counter must be reset by the falling edge of
SYNC. The user must allow 200 ns (minimum) between
successive writes.
MSB
A4 A3 A2 A1 A0
LSB
DB13–DB0
Figure 10. Serial Data Format
MICROPROCESSOR INTERFACING
AD5535 to ADSP-21xx Interface
The ADSP-21xx family of DSPs is easily interfaced to the
AD5535 without the need for extra logic. A data transfer is
initiated by writing a word to the TX register after the SPORT
has been enabled. In a write sequence, data is clocked out on
each rising edge of the DSP’s serial clock and clocked into the
AD5535 on the falling edge of its SCLK. The easiest way to
provide the 19-bit data-word required by the AD5535, is to
transmit two 10-bit data-words from the ADSP-21xx. Ensure
that the data is positioned correctly in the TX register so that
the first 19 bits transmitted contain valid data.
Set up the SPORT control register as follows:
TFSW = 1, Alternate Framing
INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = 1, Frame Every Word
ITFS = 1, Internal Framing Signal
SLEN = 1001, 10-Bit Data Word
Figure 11 shows the connection diagram.
Rev. PrE | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD5535.PDF ] | |
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