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PDF ISP1563 Data sheet ( Hoja de datos )
| Número de pieza | ISP1563 | |
| Descripción | Hi-Speed Universal Serial Bus PCI Host Controller | |
| Fabricantes | NXP Semiconductors | |
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ISP1563
www.DataSheet4U.com
Hi-Speed Universal Serial Bus PCI Host Controller
Rev. 01 — 14 July 2005
Product data sheet
1. General description
The ISP1563 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal
Serial Bus (USB) Host Controller. It integrates two Original USB Open Host Controller
Interface (OHCI) cores, one Hi-Speed USB Enhanced Host Controller Interface (EHCI)
core, and four transceivers that are compliant with Hi-Speed USB and Original USB. The
functional parts of the ISP1563 are fully compliant with Universal Serial Bus Specification
Rev. 2.0, Open Host Controller Interface Specification for USB Rev. 1.0a, Enhanced Host
Controller Interface Specification for Universal Serial Bus Rev. 1.0, PCI Local Bus
Specification Rev. 2.2, and PCI Bus Power Management Interface Specification Rev. 1.1.
The integrated high performance USB transceivers allow the ISP1563 to handle all
Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and
low-speed (1.5 Mbit/s). The ISP1563 provides four downstream ports, allowing
simultaneous connection of USB devices at different speeds.
The ISP1563 provides downstream port status indicators, green and amber LEDs, to
allow user-rich messages of the Root Hub downstream ports status, without requiring
detailed port information in the internal registers.
The ISP1563 is fully compatible with various operating system drivers, such as Microsoft
Windows standard OHCI and EHCI drivers that are present in Windows XP,
Windows 2000 and Red Hat Linux.
The ISP1563 directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can source
3.3 V. The PCI interface fully complies with PCI Local Bus Specification Rev. 2.2.
The ISP1563 is ideally suited for use in Hi-Speed USB host-enabled motherboards,
Hi-Speed USB host PCI add-on card applications, mobile applications, and embedded
solutions.
To facilitate motherboard development, the ISP1563 can use the available 48 MHz clock
signal to reduce the total cost of a solution. To reduce Electro-Magnetic Interference
(EMI), however, it is recommended that the 12 MHz crystal is used in PCI add-on card
designs.
1 page  
Philips Semiconductors
6. Pinning information
6.1 Pinning
ISP1563www.DataSheet4U.com
HS USB PCI Host Controller
1 96
ISP1563BM
32 65
Fig 2. Pin configuration.
004aaa511
6.2 Pin description
9397 750 14224
Product data sheet
Table 2: Pin description
Symbol [1] Pin Type Description
PME#
1O
PCI Power Management Event; used by a device to request a
change in the device or system power state
PCI pad; 3.3 V signaling; open-drain
GNDD
2-
digital ground
IRQ1
3O
system keyboard interrupt; when not in use, pull-down to ground
through a 10 kΩ resistor
3.3 V output pad; 3 ns slew rate control; CMOS; open-drain
IRQ12
4O
system mouse interrupt; when not in use, pull-down to ground
through a 10 kΩ resistor
3.3 V output pad; 3 ns slew rate control; CMOS; open-drain
SEL2PORTS 5 I
select two or four ports:
• LOW: four ports selected
• HIGH: two ports selected.
3.3 V input pad; push-pull; CMOS
VCC(I/O)_AUX 6
-
3.3 V auxiliary supply voltage; used to power pads; add a 100 nF
decoupling capacitor
A20OUT
7O
legacy gate 20 output; when not in use, pull-down to ground through
a 10 kΩ resistor
3.3 V output pad; 3 ns slew rate control; CMOS; open-drain
KBIRQ1
8I
legacy keyboard interrupt input; when not in use, pull-down to ground
through a 10 kΩ resistor [2]
3.3 V input pad; push-pull; CMOS
MUIRQ12 9 I
legacy mouse interrupt input; when not in use, pull-down to ground
through a 10 kΩ resistor [2]
3.3 V input pad; push-pull; CMOS
GNDA
10 -
analog ground
Rev. 01 — 14 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 107
5 Page 
Philips Semiconductors
ISP1563www.DataSheet4U.com
HS USB PCI Host Controller
Table 2: Pin description…continued
Symbol [1] Pin Type Description
PWE4_N 115 O power enable for the USB downstream port 4
3.3 V output pad; 3 ns slew rate control; CMOS; open-drain
GNDA
116 -
analog ground
DM3
117 AI/O D−; analog connection for the USB downstream port 3; leave this pin
open when not in use
GNDA
118 -
analog ground
DP3 119 AI/O D+; analog connection for the USB downstream port 3; leave this pin
open when not in use
VDDA_AUX
SEL48M
120 -
121 I
auxiliary analog supply voltage; add a 100 nF decoupling capacitor
selection between 12 MHz crystal and 48 MHz oscillator:
• LOW: 12 MHz crystal is used
• HIGH: 48 MHz clock is used.
3.3 V input pad; push-pull; CMOS
SCL
122 I/O
I2C-bus clock; pull-up to 3.3 V through a 10 kΩ resistor [3]
I2C-bus pad; clock signal
SDA
123 I/O
I2C-bus data; pull-up to 3.3 V through a 10 kΩ resistor [3]
I2C-bus pad; data signal
GNDA
124 -
analog ground
DM4
125 AI/O D−; analog connection for the USB downstream port 4; leave this pin
open when not in use
GNDA
126 -
analog ground
DP4 127 AI/O D+; analog connection for the USB downstream port 4; leave this pin
open when not in use
VDDA_AUX
128 -
auxiliary analog supply voltage; add a 100 nF decoupling capacitor
[1] Symbol names ending with ‘#’, for example, NAME#, represent active LOW signals for PCI pins. Symbol
names ending with underscore N, for example, NAME_N, represent active LOW signals for USB pins.
[2] If legacy support is not used, connect this pin to ground.
[3] Connect to ground if I2C-bus is not used.
9397 750 14224
Product data sheet
Rev. 01 — 14 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 107
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