PDF ISP1562 Data sheet ( Hoja de datos )

Número de pieza	ISP1562
Descripción	Hi-Speed Universal Serial Bus PCI Host Controller
Fabricantes	NXP Semiconductors
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No Preview Available ! ISP1562 www.DataSheet4U.com Hi-Speed Universal Serial Bus PCI Host Controller Rev. 01 — 14 July 2005 Product data sheet 1. General description The ISP1562 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal Serial Bus (USB) Host Controller. It integrates two Original USB Open Host Controller Interface (OHCI) cores, one Hi-Speed USB Enhanced Host Controller Interface (EHCI) core, and two transceivers that are compliant with Hi-Speed USB and Original USB. The functional parts of the ISP1562 are fully compliant with Universal Serial Bus Speciﬁcation Rev. 2.0, Open Host Controller Interface Speciﬁcation for USB Rev. 1.0a, Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus Rev. 1.0, PCI Local Bus Speciﬁcation Rev. 2.2, and PCI Bus Power Management Interface Speciﬁcation Rev. 1.1. The integrated high performance USB transceivers allow the ISP1562 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1562 provides two downstream ports, allowing simultaneous connection of USB devices at different speeds. The ISP1562 is fully compatible with various operating system drivers, such as Microsoft Windows standard OHCI and EHCI drivers that are present in Windows XP, Windows 2000 and Red Hat Linux. The ISP1562 directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can source 3.3 V. The PCI interface fully complies with PCI Local Bus Speciﬁcation Rev. 2.2. The ISP1562 is ideally suited for use in Hi-Speed USB mobile applications and embedded solutions. The ISP1562 uses a 12 MHz crystal. 2. Features s Complies with Universal Serial Bus Speciﬁcation Rev. 2.0 s Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) s Two Original USB OHCI cores comply with Open Host Controller Interface Speciﬁcation for USB Rev. 1.0a s One Hi-Speed USB EHCI core complies with Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus Rev. 1.0 s Supports PCI 32-bit, 33 MHz interface compliant with PCI Local Bus Speciﬁcation Rev. 2.2, with support for D3cold standby and wake-up modes; all I/O pins are 3.3 V standard s Compliant with PCI Bus Power Management Interface Speciﬁcation Rev. 1.1 for all hosts (EHCI and OHCI), and supports all power states: D0, D1, D2, D3hot and D3cold 1 page Philips Semiconductors ISP1562www.DataSheet4U.com USB PCI Host Controller 6.2 Pin description Table 2: Pin description Symbol [1] Pin Type Description GNDA 1- analog ground AUX1V8 2 - 1.8 V auxiliary output voltage; only for voltage conditioning; cannot be used to supply power to external components; connected to 100 nF and 20 µF capacitors VI(VAUX3V3) INTA# 3 4 - 3.3 V auxiliary input voltage; add a 100 nF decoupling capacitor I/O PCI interrupt PCI pad; 3.3 V signaling; open-drain RST# 5I PCI reset; used to bring PCI-speciﬁc registers, sequencers and signals to a consistent state 3.3 V input pad; push-pull; CMOS GNDD 6- digital ground PCICLK 7 I PCI system clock (33 MHz) PCI pad; 3.3 V signaling GNT# 8 I/O PCI grant; indicates to the agent that access to the bus is granted PCI pad; 3.3 V signaling REQ# 9 I/O PCI request; indicates to the arbitrator that the agent wants to use the bus PCI pad; 3.3 V signaling AD[31] 10 I/O bit 31 of multiplexed PCI address and data PCI pad; 3.3 V signaling VCC(I/O) 11 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor AD[30] 12 I/O bit 30 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[29] 13 I/O bit 29 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[28] 14 I/O bit 28 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[27] 15 I/O bit 27 of multiplexed PCI address and data PCI pad; 3.3 V signaling VI(VREG3V3) 16 GNDA 17 - - 3.3 V regulator input voltage; add a 100 nF decoupling capacitor analog ground REG1V8 18 - 1.8 V regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; connected to 100 nF and 20 µF capacitors GNDD 19 - digital ground AD[26] 20 I/O bit 26 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[25] 21 I/O bit 25 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[24] 22 I/O bit 24 of multiplexed PCI address and data PCI pad; 3.3 V signaling 9397 750 14223 Product data sheet Rev. 01 — 14 July 2005 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 5 of 98 5 Page Philips Semiconductors ISP1562www.DataSheet4U.com USB PCI Host Controller 7.7 Power-On Reset (POR) Figure 3 shows a possible curve of VCC(I/O) with dips at t2 to t3 and t4 to t5. At t0, POR will start with 1. At t1, the detector passes through the trip level. Another delay will be added before POR drops to 0 to ensure that the length of the generated detector pulse, POR, is large enough to reset asynchronous ﬂip-ﬂops. If the dip is too short (t4 to t5 < 11 µs), POR will not react and will stay LOW. t0 t1 t2 t3 VPOR(trip) is typically 1.2 V. Fig 3. Power-on reset. VCC(I/O) VPOR(trip) t4 t5 POR 004aaa664 7.8 Power supply Figure 4 shows the ISP1562 power supply connection. 9397 750 14223 Product data sheet Rev. 01 — 14 July 2005 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 11 of 98 11 Page

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