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IS61VPD102418A PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 IS61VPD102418A
部品説明 512K x 36/ 1024K x 18 18Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 



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IS61VPD102418A Datasheet, IS61VPD102418A PDF,ピン配置, 機能
IS61VPD51236A IS61VPD102418A
IS61LPD51236A IS61LPD102418A
512K x 36, 1024K x 18
18Mb SYNCHRONOUS PIPELINED,
DOUBLE CYCLE DESELECT STATIC RAM
ISSI®
www.DataSheet4U.com
FEBRUARY 2006
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Double cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LPD: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPD: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP and 165-pin PBGA
package
• Lead-free available
DESCRIPTION
The ISSI IS61LPD/VPD51236A and IS61LPD/
VPD102418Aarehigh-speed,low-powersynchronous static
RAMs designed to provide burstable, high-performance memory
for communication and networking applications. The
IS61LPD/VPD51236A is organized as 524,288 words by 36
bits, and the IS61LPD/VPD102418A is organized as
1,048,576 words by 18 bits. Fabricated with ISSI's ad-
vanced CMOS technology, the device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive capa-
bility outputs into a single monolithic circuit. All synchro-
nous inputs pass through registers controlled by a positive-
edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to four
bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
250 200 Units
2.6 3.1
ns
4 5 ns
250 200 MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/03/06
1

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IS61VPD102418A

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IS61VPD102418A

512K x 36/ 1024K x 18 18Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM

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