PDF IS61LP6436A Data sheet ( Hoja de datos )

Número de pieza	IS61LP6436A
Descripción	64K x 32- 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM
Fabricantes	Integrated Silicon Solution
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No Preview Available ! IS61LP6432A IS61LP6436A 64K x 32, 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM ® ISSIwww.DataSheet4U.com SEPTEMBER 2005 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin TQFP package • Power-down snooze mode • Power Supply: +3.3V VDD +3.3V or 2.5V VDDQ (I/O) • Lead-free available DESCRIPTION The ISSI IS61LP6432A/36A is a high-speed synchronous static RAM designed to provide a burstable, high-perfor- mance memory for high speed networking and communica- tion applications. The IS61LP6432A is organized as 64K words by 32 bits and the IS61LP6436A is organized as 64K words by 36 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high- speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -166 3.5 6 166 -133 Units 4 ns 7.5 ns 133 MHz Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 09/02/05 1 1 page IS61LP6432A IS61LP6436A ISSI ® www.DataSheet4U.co TRUTH TABLE Operation Address Used CE CE2 CE2 ADSP ADSC ADV WRITE OE DQ Deselected, Power-down None H X X X L X X X High-Z Deselected, Power-down None L X H L X X X X High-Z Deselected, Power-down None L L X L X X X X High-Z Deselected, Power-down None X X H H L X X X High-Z Deselected, Power-down None X L X H L X X X High-Z Read Cycle, Begin Burst External L H L L X X X X Q Read Cycle, Begin Burst External L H L H L X Read X Q Write Cycle, Begin Burst External L H L H L X Write X D Read Cycle, Continue Burst Next X X X H H L Read L Q Read Cycle, Continue Burst Next X X X H H L Read H High-Z Read Cycle, Continue Burst Next H X X X H L Read L Q Read Cycle, Continue Burst Next H X X X H L Read H High-Z Write Cycle, Continue Burst Next X X X H H L Write X D Write Cycle, Continue Burst Next H X X X H L Write X D Read Cycle, Suspend Burst Current X X X H H H Read L Q Read Cycle, Suspend Burst Current X X X H H H Read H High-Z Read Cycle, Suspend Burst Current H X X X H H Read L Q Read Cycle, Suspend Burst Current H X X X H H Read H High-Z Write Cycle, Suspend Burst Current X X X H H H Write X D Write Cycle, Suspend Burst Current H X X X H H Write X D PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW BWE HH HL HL HL LX BW1 X H L L X BW2 X H H L X BW3 X H H L X BW4 X H H L X Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 09/02/05 5 5 Page IS61LP6432A IS61LP6436A READ/WRITE CYCLE TIMING CLK ADSP ADSC ADV A15-A0 GW BWE tKC tKH tSS tSH tKL tSS tSH tAVS tAS tAH RD1 tWS RD2 tWH tWS tWH ISSI ® www.DataSheet4U.com ADSP is blocked by CE inactive ADSC initiate read tAVH Suspend Burst RD3 BW4-BW1 CE CE2 CE2 OE DATAOUT DATAIN tCES tCEH CE Masks ADSP tCES tCEH tCES tCEH tOEQ CE2 and CE2 only sampled with ADSP or ADSC tOEHZ High-Z High-Z tOELZ tKQLZ tKQ tOEQX 1a Single Read 2a 2b 2c 2d Burst Read Pipelined Read Unselected with CE2 tKQX 3a tKQHZ Unselected Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 09/02/05 11 11 Page

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Número de pieza	Descripción	Fabricantes
IS61LP6436A	64K x 32 or 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM	Integrated Silicon Solution
IS61LP6436A	64K x 32- 64K x 36 SYNCHRONOUS PIPELINED STATIC RAM	Integrated Silicon Solution

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