|
|
PDF CXA3314ER Data sheet ( Hoja de datos )
| Número de pieza | CXA3314ER | |
| Descripción | 6GHz PLL | |
| Fabricantes | Sony | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CXA3314ER (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
6GHz PLL
CXA3314ERwww.DataSheet4U.com
Description
The CXA3314ER is a general-purpose PLL IC
which directly frequency divides RF up to 6GHz in
combination with an external VCO and loop.
24 pin VQFN (Plastic)
Features
• Low current consumption: 9mA (typ. at VCC = 3V)
• Low voltage operation: 2.7 to 3.3V
• Small package: 24-pin VQFN (plastic)
• Supports sleep mode: 10µA (max. at VCC = 3V)
• Data setting by a 3-wire interface
• Reference frequency divider
Reference counter: 15 bits (3 to 32767)
• Comparison frequency divider
Fixed frequency division: 4
Swallow counter:
5 bits (0 to 31)
Main counter:
13 bits (3 to 8191)
Comparison frequency
division value:
4 × (992 to 262143)
• Built-in charge pump circuit with high-speed pull-in
and normal modes
• Lock signal output function
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC 3.6 V
• Operating temperature
Topr –30 to +85 °C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation PD
900 mW
Operating Condition
Supply voltage
VCC 2.7 to 3.3 V
Applications
This IC is ideal for the synthesizers of microwave
communications equipment up to 6GHz and
general-purpose PLL synthesizers such as in high-
speed, high frequency measurement equipment.
• ETC (ITS) related
• VCO modules
• Wireless LAN communications
• High-speed, high frequency measurement
equipment
Structure
Bipolar silicon monolithic IC
Note on ESD strength
This product has a low ESD strength to ensure the high frequency characteristics.
Sony semiconductor devices are classified into ESD strength ranks from A to E based on ESD test results
according to Sony original criteria.
These ESD ranks are set for each test, and indicate the ESD risk for each breakdown model.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00782E2Z-PS
1 page  
Pin Description
Pin
No.
Symbol
7 TESTDIS
8 LE
9 CLK
10 DATA
11 CEX
I/O Equivalent circuit
I
5 VDD
6
I
I IN
I
13
VSS
I 14
5 VDD
6
12 LKDET
O OUT 12
13
VSS
14
CXA3314ER
www.DataSheet4U.com
Description
Test mode switch pin.
High: Active
Low: Test mode
Latch input.
Clock input.
Data input.
Power save function pins.
High: Power save
Low: Active
Lock detection signal output.
•Active mode
High: Lock
Low: Unlock
•Test mode
Refer to “2. Test mode setting” on page 12.
–5–
5 Page 
1-3. Pull-in mode setting
CXA3314ER
www.DataSheet4U.com
The uppermost bit (F) set simultaneously with the N value and (S, I, E) of the upper 4 bits set simultaneously
with the R value are used for various settings in pull-in mode.
LSB MSB
N counter setting C1 C2
F
Control bits = [1, 0]
LSB
R counter setting C1 C2
Pull-in mode setting (F)
MSB
S∗ I E
Control bits = [0, 0]
The meaning of each bit is as follows.
Pull-in mode setting (E, I, S)
∗ Always set to "0".
F: Pull-in mode start/end flag
Pull-in mode is activated and the lock detector is cleared when the F flag is set to "1".
Pull-in mode ends when the F flag is set to "0".
E: Pull-in mode end judgment flag
Pull-in mode automatically ends when the E flag is "1" and lock is detected.
When the E flag is "0", pull-in mode continues until the F flag is set to "0".
IS: Pull-in mode flags
These flags select the high-speed pull-in method used in pull-in mode.
The various methods are active at the following timings.
Loop filter saturation reset
CP current doubled
Damping resistance value halved
When the S flag is "1".
When the I flag is "1".
When either of the S or I flags is "1".
1-4. Initialization
When the control bits [C1, C2] = [1, 1], the counter frequency division value and pull-in mode setting bits are
initialized and set to R = 40, N = 5795, F = 1, SI = 11, and E = 1. The serial input format is as follows.
LSB
C1 C2
MSB
Control bits = [1, 1]
– 11 –
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CXA3314ER.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CXA3314ER | 6GHz PLL | Sony |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |