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IS42VS16400C1 の電気的特性と機能

IS42VS16400C1のメーカーはIntegrated Silicon Solutionです、この部品の機能は「1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS42VS16400C1
部品説明 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS42VS16400C1 Datasheet, IS42VS16400C1 PDF,ピン配置, 機能
IS42VS16400C1
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
ISSI®
www.DataSheet4U.com
OCTOBER 2005
FEATURES
• Clock frequency: 100, 83, 66 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 1.8V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Industrial temperature availability
• Package: 400-mil 54-pin TSOP II
• Lead-free package is available
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42VS16400C1 is
organized as 1,048,576 bits x 16-bit x 4-bank for improved
performance. ThesynchronousDRAMsachievehigh-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
VDD
DQ0
VDDQ
DQ1
DQ2
GNDQ
DQ3
DQ4
VDDQ
DQ5
DQ6
GNDQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 GND
53 DQ15
52 GNDQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 GNDQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 GND
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 GND
PIN DESCRIPTIONS
A0-A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM
UDQM
VDD
GND
VDDQ
GNDQ
NC
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05
1

1 Page





IS42VS16400C1 pdf, ピン配列
IS42VS16400C1
ISSI ®
www.DataSheet4U.com
PIN FUNCTIONS
Symbol
A0-A11
BA0, BA1
CAS
CKE
CLK
CS
DQ0 to
DQ15
LDQM,
UDQM
RAS
WE
VDDQ
VDD
GNDQ
GND
Pin No.
Type Function (In Detail)
23 to 26
29 to 34
22, 35
Input Pin
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
20, 21
17
Input Pin
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
37
Input Pin
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode. CKE is an asynchronous input.
38
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
19
Input Pin
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
2, 4, 5, 7, 8, 10,
11,13, 42, 44, 45,
47, 48, 50, 51, 53
DQ Pin
DQ0 to DQ15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
15, 39
18
16
Input Pin
Input Pin
Input Pin
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. When LDQM or UDQM is HIGH, input data is masked and
cannot be written to the device.
RAS, in conjunction with CAS and WE, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Command
Truth Table" item for details on device commands.
3, 9, 43, 49 Power Supply Pin VDDQ is the output buffer power supply.
1, 14, 27 Power Supply Pin VDD is the device internal power supply.
6, 12, 46, 52 Power Supply Pin GNDQ is the output buffer ground.
28, 41, 54 Power Supply Pin GND is the device internal ground.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05
3


3Pages


IS42VS16400C1 電子部品, 半導体
IS42VS16400C1
ISSI ®
www.DataSheet4U.com
TRUTH TABLE – COMMANDS AND DQM OPERATION(1)
FUNCTION
CS RAS CAS WE DQM
ADDR
DQs
COMMAND INHIBIT (NOP)
HXXXX X X
NO OPERATION (NOP)
LHHHX X X
ACTIVE (Select bank and activate row)(3) L L H H X
READ (Select bank/column, start READ burst)(4)
L
H
L
H L/H(8)
WRITE (Select bank/column, start WRITE burst)(4) L H L L L/H(8)
Bank/Row
Bank/Col
Bank/Col
X
X
Valid
BURST TERMINATE
LHHL X
PRECHARGE (Deactivate row in bank or banks)(5) L L H L X
AUTO REFRESH or SELF REFRESH(6,7) L L L H X
(Enter self refresh mode)
LOAD MODE REGISTER(2)
LLLLX
Write Enable/Output Enable(8)
————
L
Write Inhibit/Output High-Z(8)
———— H
X
Code
X
Op-Code
Active
X
X
X
Active
High-Z
NOTES:
1. CKE is HIGH for all commands except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
auto precharge; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
10/06/05

6 Page



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部品番号部品説明メーカ
IS42VS16400C1

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Silicon Solution
Integrated Silicon Solution


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