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IS41C16105 の電気的特性と機能

IS41C16105のメーカーはIntegrated Silicon Solutionです、この部品の機能は「1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS41C16105
部品説明 1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS41C16105 Datasheet, IS41C16105 PDF,ピン配置, 機能
IS41C16105
IS41LV16105
www.DataSheet4U.com
1M x 16 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval: 1,024 cycles/16 ms
• Refresh Mode: RAS-Only, CAS-before-RAS (CBR),
Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% (IS41C16105)
3.3V ± 10% (IS41LV16105)
• Byte Write and Byte Read operation via two CAS
• Industrail temperature range -40oC to 85oC
DESCRIPTION
The 1+51 IS41C16105 and IS41LV16105 are 1,048,576 x
16-bit high-performance CMOS Dynamic Random Access
Memories. Fast Page Mode allows 1,024 random accesses
within a single row with access cycle time as short as 20 ns per
16-bit word. The Byte Write control, of upper and lower byte,
makes the IS41C16105 ideal for use in 16-, 32-bit wide data
bus systems.
These features make the IS41C16105 and IS41LV16105
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IS41C16105 and IS41LV16105 are packaged in a
42-pin 400mil SOJ and 400mil 44- (50-) pin TSOP-2.
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. Fast Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
-50
50
13
25
20
84
-60 Unit
60 ns
15 ns
30 ns
25 ns
104 ns
PIN CONFIGURATIONS
44(50)-Pin TSOP-2
42-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
15
16
17
18
19
20
21
22
23
24
25
50 GND
49 I/O15
48 I/O14
47 I/O13
46 I/O12
45 GND
44 I/O11
43 I/O10
42 I/O9
41 I/O8
40 NC
36 NC
35 LCAS
34 UCAS
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 GND
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 GND
41 I/O15
40 I/O14
39 I/O13
38 I/O12
37 GND
36 I/O11
35 I/O10
34 I/O9
33 I/O8
32 NC
31 LCAS
30 UCAS
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 GND
PIN DESCRIPTIONS
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR005-0C
1

1 Page





IS41C16105 pdf, ピン配列
IS41C16105
IS41LV16105
www.DataSheet4U.com
TRUTH TABLE
Function
Standby
Read: Word
Read: Lower Byte
RAS
H
L
L
LCAS
H
L
L
UCAS
H
L
H
WE
X
H
H
Read: Upper Byte
L HLH
Write: Word (Early Write)
Write: Lower Byte (Early Write)
L LLL
L LHL
Write: Upper Byte (Early Write)
L HLL
Read-Write(1,2)
Hidden Refresh
RAS-Only Refresh
CBR Refresh(4)
L
Read(2) LHL
Write(1,3) LHL
L
HL
L
L
L
H
L
L HL
LH
LL
HX
LX
OE Address tR/tC
XX
L ROW/COL
L ROW/COL
L ROW/COL
X ROW/COL
X ROW/COL
X ROW/COL
LH
L
X
X
X
ROW/COL
ROW/COL
ROW/COL
ROW/NA
X
I/O
High-Z
DOUT
Lower Byte, DOUT
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DOUT
DIN
Lower Byte, DIN
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DIN
DOUT, DIN
DOUT
DOUT
High-Z
High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Circuit Solution Inc.
DR005-0C
3


3Pages


IS41C16105 電子部品, 半導体
IS41C16105
IS41LV16105
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
www.DataSheet4U.com
Symbol Parameter
Test Condition
Speed Min.
IIL Input Leakage Current
Any input 0V < VIN < Vcc
Other inputs not under test = 0V
–5
IIO Output Leakage Current
Output is disabled (Hi-Z)
0V < VOUT < Vcc
–5
VOH Output High Voltage Level
IOH = –5.0 mA (5V)
IOH = –2.0 mA (3.3V)
2.4
VOL Output Low Voltage Level
IOL = 4.2 mA (5V)
IOL = 2.0 mA (3.3V)
—
ICC1 Standby Current: TTL
RAS, LCAS, UCAS > VIH Commerical 5V
3.3V
Extended & Idustrial 5V
3.3V
—
—
—
—
ICC2 Standby Current: CMOS
RAS, LCAS, UCAS > VCC – 0.2V
5V
3.3V
—
—
ICC3 Operating Current:
RAS, LCAS, UCAS,
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
-50 —
-60 —
ICC4 Operating Current:
RAS = VIL, LCAS, UCAS,
Fast Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
-50 —
-60 —
ICC5 Refresh Current:
RAS Cycling, LCAS, UCAS > VIH
RAS-Only(2,3)
tRC = tRC (min.)
Average Power Supply Current
-50 —
-60 —
ICC6 Refresh Current:
RAS, LCAS, UCAS Cycling
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-50 —
-60 —
Max.
5
5
—
0.4
2
1
3
2
1
0.5
160
145
90
80
160
145
160
145
Unit
µA
µA
V
V
mA
mA
mA
mA
mA
mA
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast page cycle.
5. Enables on-chip refresh and address counters.
6 Integrated Circuit Solution Inc.
DR005-0C

6 Page



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共有リンク

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部品番号部品説明メーカ
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IS41C16100S

1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Silicon Solution
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IS41C16105

1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS41C16105

1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

Integrated Silicon Solution
Integrated Silicon Solution


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