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IS41LV16100 の電気的特性と機能

IS41LV16100のメーカーはIntegrated Silicon Solutionです、この部品の機能は「1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS41LV16100
部品説明 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS41LV16100 Datasheet, IS41LV16100 PDF,ピン配置, 機能
IS41C16100
IS41LV16100
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
ISSI®
www.DataSheet4U.com
December 2005
FEATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
— Auto refresh Mode: 1,024 cycles /16 ms
RAS-Only, CAS-before-RAS (CBR), and Hidden
— Self refresh Mode - 1,024 cycles / 128ms
• JEDEC standard pinout
• Single power supply:
— 5V ± 10% (IS41C16100)
— 3.3V ± 10% (IS41LV16100)
• Byte Write and Byte Read operation via two CAS
• Industrail Temperature Range -40oC to 85oC
• Lead-free available
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II)
42-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
12
13
14
15
16
17
18
19
20
21
22
44 GND
43 I/O15
42 I/O14
41 I/O13
40 I/O12
39 GND
38 I/O11
37 I/O10
36 I/O9
35 I/O8
34 NC
33 NC
32 LCAS
31 UCAS
30 OE
29 A9
28 A8
27 A7
26 A6
25 A5
24 A4
23 GND
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 GND
41 I/O15
40 I/O14
39 I/O13
38 I/O12
37 GND
36 I/O11
35 I/O10
34 I/O9
33 I/O8
32 NC
31 LCAS
30 UCAS
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 GND
DESCRIPTION
The ISSI IS41C16100 and IS41LV16100 are 1,048,576 x 16-bit
high-performance CMOS Dynamic Random Access Memories.
These devices offer an accelerated cycle access called EDO Page
Mode. EDO Page Mode allows 1,024 random accesses within a
single row with access cycle time as short as 20 ns per 16-bit word.
The Byte Write control, of upper and lower byte, makes the
IS41C16100 ideal for use in 16-bit and 32-bit wide data bus systems.
ThesefeaturesmaketheIS41C16100andIS41LV16100ideallysuited
for high-bandwidth graphics, digital signal processing, high-
performance computing systems, and peripheral applications.
The IS41C16100 and IS41LV16100 are packaged in a 42-pin 400-
mil SOJ and 400-mil 50- (44-) pin TSOP (Type II). The lead-free 400-
mil 50- (44-) option is available too.
KEY TIMING PARAMETERS
Parameter
-50 -60 Unit
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
50 60 ns
13 15 ns
Max. Column Address Access Time (tAA) 25 30 ns
Min. EDO Page Mode Cycle Time (tPC) 20 25 ns
Min. Read/Write Cycle Time (tRC)
84 104 ns
PIN DESCRIPTIONS
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
IIntegrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. L
12/22/05
1

1 Page





IS41LV16100 pdf, ピン配列
IS41C16100
IS41LV16100
ISSI®
www.DataSheet4U.com
TRUTH TABLE
Function
Standby
Read: Word
Read: Lower Byte
RAS LCAS UCAS WE
HHHX
L L LH
L LHH
OE Address tR/tC
XX
L ROW/COL
L ROW/COL
Read: Upper Byte
L H L H L ROW/COL
Write: Word (Early Write)
Write: Lower Byte (Early Write)
L L L L X ROW/COL
L L H L X ROW/COL
Write: Upper Byte (Early Write)
L H L L X ROW/COL
Read-Write(1,2)
L L L HL LH ROW/COL
EDO Page-Mode Read(2) 1stCycle:
2nd Cycle:
Any Cycle:
L HL HL H L ROW/COL
L HL HL H
L
NA/COL
L LH LH H
L
NA/NA
EDO Page-Mode Write(1) 1stCycle:
2nd Cycle:
L HL HL L X ROW/COL
L HL HL L
X
NA/COL
EDO Page-Mode(1,2)
Read-Write
1st Cycle:
2nd Cycle:
L HL HL HL LH ROW/COL
L HL HL HL LH
NA/COL
Hidden Refresh
RAS-Only Refresh
Read(2)
LHL L
L
H
L
ROW/COL
Write(1,3)
LHL L
L
L
X ROW/COL
LHHXX
ROW/NA
CBR Refresh(4)
HL L L X X
X
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
I/O
High-Z
DOUT
Lower Byte, DOUT
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DOUT
DIN
Lower Byte, DIN
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DIN
DOUT, DIN
DOUT
DOUT
DOUT
DIN
DIN
DOUT, DIN
DOUT, DIN
DOUT
DOUT
High-Z
High-Z
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. L
12/22/05
3


3Pages


IS41LV16100 電子部品, 半導体
IS41C16100
IS41LV16100
ISSI®
www.DataSheet4U.com
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max. Unit
IIL Input Leakage Current
Any input 0V VIN Vcc
Other inputs not under test = 0V
–5 5 µA
IIO Output Leakage Current
Output is disabled (Hi-Z)
0V VOUT Vcc
–5 5 µA
VOH Output High Voltage Level
IOH = –5.0 mA (5V)
IOH = –2.0 mA (3.3V)
2.4 —
V
VOL Output Low Voltage Level
ICC1 Standby Current: TTL
IOL = 4.2 mA (5V)
IOL = 2.0 mA (3.3V)
RAS, LCAS, UCAS VIH
Commerical
Industrial
5V
3.3V
5V
3.3V
0.4 V
3 mA
3
4 mA
4
ICC2 Standby Current: CMOS
RAS, LCAS, UCAS VCC – 0.2V
5V
3.3V
2 mA
2
ICC3 Operating Current:
RAS, LCAS, UCAS,
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
ICC4 Operating Current:
RAS = VIL, LCAS, UCAS,
EDO Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
-50 — 160 mA
-60 — 145
-50 —
-60 —
90 mA
80
ICC5 Refresh Current:
RAS Cycling, LCAS, UCAS VIH
RAS-Only(2,3)
tRC = tRC (min.)
Average Power Supply Current
-50 — 160 mA
-60 — 145
ICC6 Refresh Current:
RAS, LCAS, UCAS Cycling
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-50 — 160 mA
-60 — 145
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. L
12/22/05

6 Page



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共有リンク

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部品番号部品説明メーカ
IS41LV16100

1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Silicon Solution
Integrated Silicon Solution
IS41LV16100A

1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Silicon Solution
Integrated Silicon Solution
IS41LV16100B

1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Silicon Solution
Integrated Silicon Solution
IS41LV16100S

1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Silicon Solution
Integrated Silicon Solution


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