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PDF ISL6424 Data sheet ( Hoja de datos )
| Número de pieza | ISL6424 | |
| Descripción | Single Output LNB Supply and Control Voltage Regulator | |
| Fabricantes | Intersil | |
| Logotipo |  |
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®
Data Sheet
September 13, 2005
ISL6424
www.DataSheet4U.com
FN9175.3
Dual Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-Top Box Designs
The ISL6424 is a highly integrated voltage regulator and
interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of two antenna
ports. The device is comprised of two independent current-
mode boost PWMs and two low-noise linear regulators along
with the circuitry required for 22kHz tone generation,
modulation and I2C device interface. The device makes the
total LNB supply design simple, efficient and compact with
low external component count.
Two independent current-mode boost converters provide the
linear regulators with input voltages that are set to the final
output voltages, plus typically 1.2V to insure minimum power
dissipation across each linear regulator. This maintains
constant voltage drops across each linear pass element
while permitting adequate voltage range for tone injection.
The final regulated output voltages are available at two
output terminals to support simultaneous operation of two
antenna ports for dual tuners. The outputs for each PWM are
set to 13V or 18V by independent voltage select commands
(VSEL1, VSEL2) through the I2C bus. Additionally, to
compensate for the voltage drop in the coaxial cable, the
selected voltage may be increased by 1V with the line length
compensation (LLC) feature. All the functions on this IC are
controlled via the I2C bus by writing 8 bits on System
Register (SR, 8 bits). The same register can be read back,
and two bits will report the diagnostic status. Separate enable
commands sent on the I2C bus provide independent standby
mode control for each PWM and linear combination, disabling
the output into shutdown mode.
Each output channel is capable of providing 750mA of
continuous current. The overcurrent limit can be digitally
programmed. The SEL18V pin allows the 13V to 18V
transition with an external pin, overriding the I2C input.
The ISL6424 is offered in a 32 Ld 5x5 QFN.
Features
• Single Chip Power Solution
- True Dual Operation for 2-Tuner/2-Dish Applications
- Both Outputs May be Enabled Simultaneously at
Maximum Power
- Integrated DC-DC Converter and I2C Interface
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with > 92% Efficiency
- Selectable 13V or 18V Outputs
- Digital Cable Length Compensation (1V)
• I2C Compatible Interface for Remote Device Control
- Registered Slave Address 0001 00XX
- Full 3.3V/5V Operation up to 400kHz
• External Pins to Select 13V/18V Option
• DSQIN1&2 and SEL18V1&2 pins 2.5V Logic Compatible
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC (EUTELSAT) Encoding
• Internal Over-Temperature Protection and Diagnostics
• Internal Overload and Overtemp Flags (Visible on I2C)
• LNB Short-Circuit Protection and Diagnostics
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
References
• Tech Brief 389 (TB389) - “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”; Available
on the Intersil website, www.intersil.com
Ordering Information
PART # *
PART
TEMP.
PKG.
MARKING (°C) PACKAGE DWG. #
ISL6424ER
ISL6424ER -20 to 85 32 Ld 5x5 QFN L32.5x5
ISL6424ERZ (Note) ISL6424ERZ -20 to 85 32 Ld 5x5 QFN L32.5x5
(Pb-free)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6424
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range
(SDA, SCL, ENT, DSQIN 1&2, SEL18V 1&2) . . . . . . -0.5V to 7V
Thermal Information
www.DataSheet4U.com
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
32
4
Maximum Junction Temperature (Note 3) . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . -20°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. The device junction temperature should be kept below 150°C. Thermal shut-down circuitry turns off the device if junction temperature exceeds
+150°C typically.
Electrical Specifications
VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. EN1 = EN2 = H,
LLC1 = LLC2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, Iout = 12mA, unless otherwise noted.
See software description section for I2C access to the system.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Operating Supply Voltage Range
8 12 14
V
Standby Supply Current
EN1 = EN2 = L
- 1.5 3.0 mA
Supply Current
IIN EN1 = EN2 = LLC1 = LLC2 = VSEL1 =
VSEL2 = ENT1 = ENT2 = H, No Load
-
4.0 8.0
mA
UNDERVOLTAGE LOCKOUT
Start Threshold
7.5 - 7.95 V
Stop Threshold
7.0 - 7.55 V
Start to Stop Hysteresis
350 400 500
mV
SOFT-START
COMP Rise Time (Note 4)
(Note 5)
- 512 - Cycles
Output Voltage (Note 5)
Line Regulation
Load Regulation
Dynamic Output Current Limiting
VO1
VO1
VO1
VO1
VO2
VO2
VO2
VO2
DVO1,
DVO2
DVO1,
DVO2
IMAX
VSEL1 = L, LLC1 = L
VSEL1 = L, LLC1 = H
VSEL1 = H, LLC1 = L
VSEL1 = H, LLC1 = H
VSEL2 = L, LLC2 = L
VSEL2 = L, LLC2 = H
VSEL2 = H, LLC2 = L
VSEL2 = H, LLC2 = H
VIN = 8V to 14V; VO1, VO2 = 13V
VIN = 8V to 14V; VO1, VO2 = 18V
IO = 12mA to 350mA
IO = 12mA to 750mA (Note 6)
DCL = L, ISEL1/2 = L
DCL = L, ISEL1/2 = H (Note 6)
12.74 13.0 13.26
13.72 14.0 14.28
17.64 18.0 18.36
18.62 19.0 19.38
12.74 13.0 13.26
13.72 14.0 14.28
17.64 18.0 18.36
18.62 19.0 19.38
- 4.0 40.0
- 4.0 60.0
- 50 80
- 100 200
425 - 550
775 850 950
V
V
V
V
V
V
V
V
mV
mV
mV
mV
mA
mA
Dynamic Overload Protection Off Time
TOFF DCL = L, Output Shorted (Note 6)
- 900 -
ms
Dynamic Overload Protection On Time
TON
- 20 -
ms
5 FN9175.3
September 13, 2005
5 Page 
ISL6424
Received Data (I2C bus READ MODE)
The ISL6424 can provide to the master a copy of the system
register information via the I2C bus in read mode. The read
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6424 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
• Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6424.
• Not acknowledge, stopping the read mode
communication.
While the whole register is read back by the microprocessor,
the read-only bits OLF1, OLF2, and OTF convey diagnostic
information about the ISL6424.
Power-On I2C Interface Reset
The I2C interface built into the ISL6424 is automatically reset
at power-on. The I2C interface block will receive a Power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I2Cwwcowm.DmaatandShseaentd4Uth.ceom
system register SR1 and SR2 are initialized to all zeros, thus
keeping the power blocks disabled. Once the Vcc rises
above UVLO, the POWER OK signal given to the I2C
interface block will be HIGH, the I2C interface becomes
operative and the SRs can be configured by the main
microprocessor. About 400mV of hysteresis is provided in
the UVLO threshold to avoid false triggering of the Power-
On reset circuit. (I2C comes up with EN = 0; EN goes HIGH
at the same time as (or later than) all other I2C data for that
PWM becomes valid).
ADDRESS Pin
Connecting this pin to GND the chip I2C interface address is
0001000, but, it is possible to choose between two different
addresses simply by setting this pin at one of the two fixed
voltage levels as shown in Table 8.
TABLE 6. ADDRESS PIN CHARACTERISTICS
VADDR
VADDR-1
“0001000”
MINIMUM
0V
TYPICAL
-
MAXIMUM
2V
VADDR-2
“0001001”
2.7V
- 5V
TABLE 7. READING SYSTEM REGISTERS
DCL ISEL1/2 ENT1/2 LLC1/2 VSEL1/1 EN1/2 OTF2 OLF1/2
FUNCTION
These bits are read as they were after the last write operation.
0
1
TJ ≤ 130°C, normal operation
TJ > 150°C, power blocks disabled
0 IOUT < IMAX, normal operation
1 IOUT > IMAX, overload protection triggered
I2C Electrical Characteristics
PARAMETER
Input Logic High, VIH
TABLE 8. I2C SPECIFICATIONS
TEST CONDITION
MINIMUM
SDA, SCL
TYPICAL
0.7 x VDD
MAXIMUM
Input Logic Low, VIL
Input Logic Current, IIL
SCL Clock Frequency
SDA, SCL
SDA, SCL;
0.4V < VIN < 4.5V
0
0.3 x VDD
100kHz
10µA
400kHz
11 FN9175.3
September 13, 2005
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL6424.PDF ] | |
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