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PDF ISL6425 Data sheet ( Hoja de datos )
| Número de pieza | ISL6425 | |
| Descripción | Single Output LNB Supply and Control Voltage Regulator | |
| Fabricantes | Intersil | |
| Logotipo |  |
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®
Data Sheet
February 8, 2005
ISL6425
www.DataSheet4U.com
FN9176.1
Single Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-top Box Designs
The ISL6425 is a highly integrated solution for supplying
power and control signals from advanced satellite set-top
box (STB) modules to the low noise block (LNB). This device
is comprised of a current-mode boost PWM and a low-noise
linear regulator, along with the circuitry required for I2C
device interfacing and for providing DiSEqC standard control
signals to the LNB.
A regulated output voltage is available at the output terminal
(VOUT) to support the operation of the antenna port in
advanced satellite STB applications. The regulated output
may be set to either 13V or 18V by use of the voltage select
command (VSEL) through the I2C bus. Additionally, to
compensate for the voltage drop in the coaxial cable, the
voltage may be increased by 1V with the line length
compensation (LLC) feature. An enable command sent on
the I2C bus provides standby mode control for the PWM and
linear combination, disabling the output to conserve power.
A current-mode boost converter provides the linear regulator
with an input voltage that is set to the required output
voltage, plus 1.2V (typ.) to insure minimum power
dissipation. This maintains a constant voltage drop across
the linear pass element, while permitting an adequate
voltage range for tone injection.
The device is capable of providing 750mA (typ.).
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6425ER
-20 to 85 32 Ld 5x5 QFN L32.5x5
ISL6425ER-T
32 Ld 5x5 QFN Tape and Reel L32.5x5
ISL6425ERZ
(Note)
-20 to 85
32 Ld 5x5 QFN L32.5x5
(Pb-free)
ISL6425ERZ-T
(Note)
32 Ld 5x5 QFN Tape and Reel
(Pb-free)
L32.5x5
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWM with >92% Efficiency
- Selectable 13V or 18V Outputs
- Digital Cable Length Compensation (1V)
• External Pin to Select 13V/18V Options
• DSQIN and SEL18V pins are 2.5V logic compatible
• I2C Compatible Interface for Remote Device Control
- Registered Slave Address 0001 00XX
- Fully Functional 3.3V, 5V Operation up to 400kHz
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC (EUTELSAT) Encoding
• Internal Over-Temperature Protection and Diagnostics
• Internal Overload and Overtemp Flags (Visible on I2C)
• LNB Short-Circuit Protection and Diagnostics
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint
• Pb-free available (RoHS Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
References
• Tech Brief 389 (TB389) - “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”; Available
on the Intersil website, www.intersil.com
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6425
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range
(SDA, SCL, ENT, DSQIN, SEL18V) . . . . . . . . . . . . . . -0.5V to 7V
Output Current . . . . . . . . . . . . . . . . . . . . Externally/Internally Limited
Thermal Information
www.DataSheet4U.com
Thermal Resistance
θJA (°C/W) θJC (°C/W)
QFN Package (Notes 1, 2) . . . . . . . .
32
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
NOTE: The device junction temperature should be kept below
150°C. Thermal shut-down circuitry turns off the device if junction
temperature exceeds +150°C typically.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temperature” location is the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
VCC
ENT
=
=
12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. EN = H, LLC =
L, DCL = L, DSQIN = L, IOUT = 12mA, unless otherwise noted. See software description section for
L,
I2C
access to the system.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Operating Supply Voltage Range
8 12 14
V
Standby Supply Current
EN = L
- 1.5 3.0 mA
Supply Current
UNDERVOLTAGE LOCKOUT
IIN EN = LLC = VSEL = ENT = H, No Load
-
4.0 8.0
mA
Start Threshold
7.5 - 7.95 V
Stop Threshold
7.0 - 7.55 V
Start to Stop Hysteresis
350 400 500
mV
SOFT-START
COMP Rise Time (Note 2)
(Note 4)
- 1024 - Cycles
OUTPUT VOLTAGE
Output Voltage (Note 3)
Line Regulation
Load Regulation
Dynamic Output Current Limiting
VOUT
VOUT
VOUT
VOOU
DVOUT
DVOUT
IMAX
VSEL = L, LLC = L
VSEL = L, LLC = H
VSEL = H, LLC = L
VSEL = H, LLC = H
VIN = 8V to 14V; VOUT = 13V
VIN = 8V to 14V; VOUT = 18V
IO = 12mA to 450mA
DCL = L, ISEL = L
DCL = L, ISEL = H
12.74 13.0 13.26
13.72 14.0 14.28
17.64 18.0 18.36
18.62 19.0 19.38
- 4.0 40.0
- 4.0 60.0
- 50 80
425 - 550
775 - 950
V
V
V
V
mV
mV
mV
mA
mA
Dynamic Overload Protection Off Time
TOFF DCL = L, Output Shorted (Note 4)
- 900 -
ms
Dynamic Overload Protection On Time
TON
- 20 -
ms
22kHz TONE
Tone Frequency
Tone Amplitude
Tone Duty Cycle
Tone Rise or Fall Time
ftone
Vtone
dctone
Tr, Tf
ENT = H
ENT = H
ENT = H (Note 5)
ENT = H
20.0 22.0 24.0
550 680 900
40 50 60
5 8 14
kHz
mV
%
µs
5 FN9176.1
February 8, 2005
5 Page 
ISL6425
Once Vcc rises above the UVLO level, the POWER OK
signal given to the I2C interface block will be HIGH, the I2C
interface becomes operative and the SR can be configured
by the main microprocessor. About 400mV of hysteresis is
provided in the UVLO threshold to avoid false triggering of
the Power-On reset circuit.
(I2C comes up with EN = 0, EN goes HIGH at the same time
as (or later than) all other I2C data for the PWM becomes
valid).
ADDRESS Pin
Connecting this pin to GND forces the chip I2C interface
address to 0001000; applying a voltage >2.7V forces the
address to 0001001, as shown below.
TABLE 7. ADDRESS PIN CHARACTERISTICS
VADDR MIN TYP MAX
Vaddr-1
“0001000”
Vaddr-2
“0001001”
0V
2.7V
- 2.0V
- 5.0V
I2C Electrical Characteriswtwiwc.sDataSheet4U.com
TABLE 8. I2C SPECIFICATIONS
PARAMETER
TEST
CONDITION
MIN TYP
MAX
Input Logic High, SDA, SCL
VIH
0.7 x VDD
Input Logic Low, SDA, SCL
VIL
0.3 x VDD
Input Logic
Current, IIL
SDA, SCL;
0.4V < Vin < 4.5V
10µA
SCL Clock
Frequency
0 100kHz 400kHz
11 FN9176.1
February 8, 2005
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL6425.PDF ] | |
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