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IS41LV4400x の電気的特性と機能

IS41LV4400xのメーカーはIntegrated Silicon Solutionです、この部品の機能は「4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS41LV4400x
部品説明 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS41LV4400x Datasheet, IS41LV4400x PDF,ピン配置, 機能
IS41C4400X
IS41LV4400X SERIES
4M x 4 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
ISSI®
www.DataSheet4U.com
JUNE, 2001
FEATURES
Extended Data-Out (EDO) Page Mode access cycle
TTL compatible inputs and outputs
Refresh Interval:
– 2,048 cycles/32 ms
– 4,096 cycles/64 ms
Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
Single power supply:
– 5V±10% or 3.3V ± 10%
Byte Write and Byte Read operation via two CAS
Industrial temperature range -40°C to 85°C
DESCRIPTION
The ISSI 4400 Series is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 2,048 or 4096
random accesses within a single row with access cycle
time as short as 20 ns per 4-bit word.
These features make the 4400 Series ideally suited for
high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The 4400 Series is packaged in a 24-pin 300-mil SOJ with
JEDEC standard pinouts.
PRODUCT SERIES OVERVIEW
Part No.
IS41C44002
IS41C44004
IS41LV44002
IS41LV44004
Refresh
2K
4K
2K
4K
Voltage
5V ± 10%
5V ± 10%
3.3V ± 10%
3.3V ± 10%
KEY TIMING PARAMETERS
Parameter
RAS Access Time (tRAC)
CAS Access Time (tCAC)
Column Address Access Time (tAA)
EDO Page Mode Cycle Time (tPC)
Read/Write Cycle Time (tRC)
-50
50
13
25
20
84
-60 Unit
60 ns
15 ns
30 ns
25 ns
104 ns
PIN CONFIGURATION
24 Pin SOJ
VCC
I/O0
I/O1
WE
RAS
*A11(NC)
1
2
3
4
5
6
A10
A0
A1
A2
A3
VCC
7
8
9
10
11
12
24 GND
23 I/O3
22 I/O2
21 CAS
20 OE
19 A9
18 A8
17 A7
16 A6
15 A5
14 A4
13 GND
PIN DESCRIPTIONS
A0-A11
A0-A10
I/O0-3
WE
OE
RAS
CAS
Vcc
GND
NC
Address Inputs (4K Refresh)
Address Inputs (2K Refresh)
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
* A11 is NC for 2K Refresh devices.
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/24/01
1

1 Page





IS41LV4400x pdf, ピン配列
IS41C4400X
IS41LV4400X SERIES
Functional Description
The IS41C4400x and IS41LV4400x are CMOS
DRAMs optimized for high-speed bandwidth, low
power applications. During READ or WRITE cycles, each
bit is uniquely addressed through the 11 or 12 address
bits. These are entered 11 bits (A0-A10) at a time for the
2K refresh device or 12 bits (A0-A11) at a time for the 4K
refresh device. The row address is latched by the Row
Address Strobe (RAS). The column address is latched by
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time
specified by tAR. Data Out becomes valid only when tRAC,
tAA, tCAC and tOEA are all satisfied. As a result, the access
time is dependent on the timing relationships between
these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
ISSI ®
www.DataSheet4U.com
Auto Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period, or 4,096 refresh cycles are required in
each 64ms period. There are two ways to refresh the
memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) or 4096 row addresses (A0 through
A11) with RAS at least once every 32 ms or 64ms
respectively. Any read, write, read-modify-write or
RAS-only cycle refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS
refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the VCC supply, an initial pause of 200
µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a RAS
signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. D
06/24/01
3


3Pages


IS41LV4400x 電子部品, 半導体
IS41C4400X
IS41LV4400X SERIES
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tRC
tRAC
tCAC
tAA
tRAS
tRP
tCAS
tCP
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
tRAD
tRAL
tRPC
tRSH
tRHCP
tCLZ
tCRP
tOD
tOE
tOED
tOEHC
tOEP
tOES
tRCS
tRRH
tRCH
tWCH
tWCR
tWP
tWPZ
Parameter
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
RAS Precharge Time
CAS Pulse Width(23)
CAS Precharge Time(9)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
Column-Address Hold Time
(referenced to RAS)
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 24)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 24)
Output Enable Time(15, 16)
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
Read Command Hold Time
(referenced to RAS)(12)
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17)
Write Command Hold Time
(referenced to RAS)(17)
Write Command Pulse Width(17)
WE Pulse Widths to Disable Outputs
-50
Min. Max.
84
50
13
25
50 10K
30
8 10K
9
38
12 37
0
8
0
8
30
10 25
25
5
8
30
0
5
3 15
12
12
5
10
5
0
0
0
8
40
8
7
ISSI ®
www.DataSheet4U.com
-60
Min. Max.
104
60
15
30
60 10K
40
10 10K
9
40
14 45
0
10
0
10
40
12 30
30
5
10
35
0
5
3 15
15
15
5
10
5
0
0
0
10
50
10
7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. D
06/24/01

6 Page



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共有リンク

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部品番号部品説明メーカ
IS41LV44002B

4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Silicon Solution
Integrated Silicon Solution
IS41LV4400x

4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Silicon Solution
Integrated Silicon Solution


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