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IS61VPS12836A の電気的特性と機能

IS61VPS12836AのメーカーはIntegrated Silicon Solutionです、この部品の機能は「128K x 32/ 128K x 36/ 256K x 18 4 Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61VPS12836A
部品説明 128K x 32/ 128K x 36/ 256K x 18 4 Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS61VPS12836A Datasheet, IS61VPS12836A PDF,ピン配置, 機能
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSIwww.DataSheet4U.com
128K x 32, 128K x 36, 256K x 18
4 Mb SYNCHRONOUS PIPELINED,
PRELIMINARY INFORMATION
FEBRUARY 2005
SINGLE CYCLE DESELECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP, 119-ball PBGA, and
165-ball PBGA packages
• Automotive temperature available
• Lead Free available
DESCRIPTION
The ISSIIS61(64)LPS12832A,IS61(64)LPS/VPS12836A
and IS61(64)LPS/VPS25618A are high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and network-
ing applications. The IS61(64)LPS12832A is organized as
131,072 words by 32 bits. The IS61(64)LPS/VPS12836A
isorganizedas131,072 wordsby36bits.TheIS61(64)LPS/
VPS25618A is organized as 262,144 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology, the
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single mono-
lithic circuit. All synchronous inputs pass through regis-
ters controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
250 200 Units
2.6 3.1
ns
4 5 ns
250 200 MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
1

1 Page





IS61VPS12836A pdf, ピン配列
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
165-PIN BGA
165-Ball, 13x15 mm BGA
1mm Ball Pitch, 11x15 Ball Array
ISSI ®
www.DataSheet4U.com
119-PIN BGA
119-Ball, 14x22 mm BGA
1mm Ball Pitch, 7x17 Ball Array
BOTTOM VIEW
BOTTOM VIEW
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
3


3Pages


IS61VPS12836A 電子部品, 半導体
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI ®
www.DataSheet4U.com
165 PBGA PACKAGE PIN CONFIGURATION
128K X 36 (TOP VIEW)
1
A NC
B NC
2
A
A
3
CE
CE2
4
BWc
BWd
5
BWb
BWa
6
CE2
CLK
7
BWE
GW
8
ADSC
OE
9
ADV
ADSP
10
A
A
11
NC
NC
C DQPc NC
VDDQ
Vss
Vss
Vss
Vss
Vss
VDDQ NC DQPb
D DQc
DQc
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
E DQc
DQc
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
F DQc
DQc
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
G DQc
DQc
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQb
DQb
H NC NC NC VDD Vss Vss Vss VDD NC NC ZZ
J DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
K DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
L DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
M DQd
DQd
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
DQa
N DQPd NC
VDDQ
Vss
NC
NC
NC
Vss
VDDQ
NC
DQPa
P NC NC A A NC A1* NC A A A NC
R MODE NC
A
A
NC A0* NC A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
A Address Inputs
A0, A1
ADV
ADSP
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
ADSC
GW
Address Status Controller
Global Write Enable
CLK
CE, CE2, CE2
BWx (x=a,b,c,d)
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write
Controls
Symbol
BWE
OE
ZZ
MODE
NC
DQx
DQPx
VDD
VDDQ
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V/2.5V
Ground
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04

6 Page



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部品番号部品説明メーカ
IS61VPS12836A

128K x 32/ 128K x 36/ 256K x 18 4 Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution
Integrated Silicon Solution
IS61VPS12836A

128K x 32 / 128K x 36- 256K x 18 4Mb SYNCHRONOUS PIPELINED / SINGLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution
Integrated Silicon Solution
IS61VPS12836EC

SINGLE CYCLE DESELECT SRAM

ISSI
ISSI


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