IS61LPS25618A Datasheet PDF - Integrated Silicon Solution
| Part Number | IS61LPS25618A | |
| Description | 128K x 32/ 128K x 36/ 256K x 18 4 Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM | |
| Manufacturers | Integrated Silicon Solution | |
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There is a preview and IS61LPS25618A download ( pdf file ) link at the bottom of this page. Total 26 Pages | ||
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IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
®
ISSIwww.DataSheet4U.com
128K x 32, 128K x 36, 256K x 18
4 Mb SYNCHRONOUS PIPELINED,
PRELIMINARY INFORMATION
FEBRUARY 2005
SINGLE CYCLE DESELECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP, 119-ball PBGA, and
165-ball PBGA packages
• Automotive temperature available
• Lead Free available
DESCRIPTION
The ISSIIS61(64)LPS12832A,IS61(64)LPS/VPS12836A
and IS61(64)LPS/VPS25618A are high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and network-
ing applications. The IS61(64)LPS12832A is organized as
131,072 words by 32 bits. The IS61(64)LPS/VPS12836A
isorganizedas131,072 wordsby36bits.TheIS61(64)LPS/
VPS25618A is organized as 262,144 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology, the
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single mono-
lithic circuit. All synchronous inputs pass through regis-
ters controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
250 200 Units
2.6 3.1
ns
4 5 ns
250 200 MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
1
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IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
ISSI ®
www.DataSheet4U.com
119 BGA PACKAGE PIN CONFIGURATION
256KX18 (TOP VIEW)
1 2 3 4 5 67
A VDDQ
B NC
A
CE2
A ADSP A
A ADSC A
A
CE2
VDDQ
NC
C NC
A
A VDD A
A NC
D DQb
E NC
F VDDQ
G NC
H DQb
NC
DQb
NC
DQb
NC
Vss
Vss
Vss
BWb
Vss
NC
CE
OE
ADV
GW
Vss DQPa NC
Vss NC DQa
Vss
DQa
VDDQ
Vss NC DQa
Vss DQa NC
J VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K NC
DQb Vss CLK Vss
NC DQa
L DQb
NC
Vss
NC
BWa
DQa NC
M VDDQ DQb Vss BWE Vss
NC VDDQ
N DQb NC Vss A1* Vss DQa NC
P
NC
DQPb
Vss
A0*
Vss
NC DQa
R NC
A
MODE
VDD
NC
A NC
T NC
A
A NC A
A ZZ
U VDDQ
NC
NC
NC
NC
NC VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2, CE2
BWx (x=a,b)
BWE
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write Controls
Byte Write Enable
Symbol
OE
ZZ
MODE
NC
DQa-DQb
DQPa-Pb
VDD
VDDQ
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
10/07/04
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IS61LPS25618A electronic component. |
| Information | Total 26 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IS61LPS25618A.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| IS61LPS25618A | The function is 128K x 32/ 128K x 36/ 256K x 18 4 Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM. Integrated Silicon Solution | |
| IS61LPS25618A | The function is 128K x 32 / 128K x 36- 256K x 18 4Mb SYNCHRONOUS PIPELINED / SINGLE CYCLE DESELECT STATIC RAM. Integrated Silicon Solution | |
| IS61LPS25618EC | The function is SINGLE CYCLE DESELECT SRAM. ISSI |  |
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