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IS61VPS204818A の電気的特性と機能

IS61VPS204818AのメーカーはIntegrated Silicon Solutionです、この部品の機能は「1Mb x 36 - 2Mb x 18 36Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61VPS204818A
部品説明 1Mb x 36 - 2Mb x 18 36Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS61VPS204818A Datasheet, IS61VPS204818A PDF,ピン配置, 機能
IS61VPS102436A IS61LPS102436A
IS61VPS204818A IS61LPS204818A
1Mb x 36, 2Mb x 18
36Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
www.DataSheet4U.com
MARCH 2008
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP and 165-ball PBGA
packages
• Lead-free available
DESCRIPTION
The ISSI IS61LPS/VPS102436A and IS61LPS/VPS
204818A are high-speed, low-power synchronous static
RAMs designed to provide burstable, high-performance memory
for communication and networking applications. The
IS61LPS/VPS102436A is organized as 1,048,476 words
by 36 bits. The IS61LPS/VPS204818A is organized as
2M-word by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
200 166 Units
3.1 3.5 ns
5 6 ns
200 166 MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
1

1 Page





IS61VPS204818A pdf, ピン配列
IS61VPS102436A, IS61LPS102436A,IS61VPS204818A,IS61LPS204818A
www.DataSheet4U.com
165-PIN BGA
165-Ball, 13x15 mm BGA
1mm Ball Pitch, 11x15 Ball Array
BOTTOM VIEW
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
3


3Pages


IS61VPS204818A 電子部品, 半導体
IS61VPS102436A, IS61LPS102436A,IS61VPS204818A,IS61LPS204818A
www.DataSheet4U.com
PIN CONFIGURATION
100-PIN TQFP
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
1M x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A Synchronous Address Inputs
ADSC
Synchronous Controller Address
Status
ADSP
Synchronous Processor Address
Status
ADV
Synchronous Burst Address Advance
BWa-BWd
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK Synchronous Clock
6
DQa-DQd
DQPa-DQPd
GW
MODE
OE
VDD
VDDQ
Vss
ZZ
Synchronous Data Input/Output
Parity Data Input/Output
Synchronous Global Write Enable
Burst Sequence Mode Selection
Output Enable
3.3V/2.5V Power Supply
Isolated Output Buffer Supply:
3.3V/2.5V
Ground
Snooze Enable
Integrated Silicon Solution, Inc.
Rev. B
03/27/08

6 Page



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共有リンク

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部品番号部品説明メーカ
IS61VPS204818A

1Mb x 36 - 2Mb x 18 36Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution
Integrated Silicon Solution
IS61VPS204818A

1MB x 36/ 2Mb x 18 36Mb SYNCHRONOUS PIPELINED / SINGLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution
Integrated Silicon Solution


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