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PDF IS61LPS204818A Data sheet ( Hoja de datos )
| Número de pieza | IS61LPS204818A | |
| Descripción | 1Mb x 36 - 2Mb x 18 36Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM | |
| Fabricantes | Integrated Silicon Solution | |
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IS61VPS102436A IS61LPS102436A
IS61VPS204818A IS61LPS204818A
1Mb x 36, 2Mb x 18
36Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
www.DataSheet4U.com
MARCH 2008
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP and 165-ball PBGA
packages
• Lead-free available
DESCRIPTION
The ISSI IS61LPS/VPS102436A and IS61LPS/VPS
204818A are high-speed, low-power synchronous static
RAMs designed to provide burstable, high-performance memory
for communication and networking applications. The
IS61LPS/VPS102436A is organized as 1,048,476 words
by 36 bits. The IS61LPS/VPS204818A is organized as
2M-word by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
200 166 Units
3.1 3.5 ns
5 6 ns
200 166 MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
1
1 page  
IS61VPS102436A, IS61LPS102436A,IS61VPS204818A,IS61LPS204818A
www.DataSheet4U.com
165 PBGA PACKAGE PIN CONFIGURATION
2M X 18 (TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11
A NC
A
CE
BWb
NC
CE2
BWE ADSC ADV
A
A
B NC
A
CE2
NC
BWa
CLK
GW
OE
ADSP A
NC
C NC
NC
VDDQ
Vss
Vss
Vss
Vss
Vss
VDDQ
NC
DQPa
D NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
E NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
F NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
G NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
H NC NC NC VDD Vss Vss Vss VDD NC NC ZZ
J
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
K DQb NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
L DQb NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
M DQb NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
N DQPb NC
VDDQ
Vss
NC
A
NC
Vss
VDDQ
NC
NC
P NC NC A A NC A1* NC A A A A
R MODE A A A NC A0* NC A A A A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2, CE2
BWx (x=a,b)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write
Controls
Symbol
BWE
OE
ZZ
MODE
NC
DQx
DQPx
VDD
VDDQ
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V/2.5V
Ground
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
5
5 Page 
IS61VPS102436A, IS61LPS102436A,IS61VPS204818A,IS61LPS204818A
www.DataSheet4U.com
OPERATING RANGE (IS61LPSXXXXX)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VDD
3.3V + 5%
3.3V + 5%
VDDQ
3.3V / 2.5V + 5%
3.3V / 2.5V + 5%
OPERATING RANGE (IS61VPSXXXXX)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VDD
2.5V + 5%
2.5V + 5%
VDDQ
2.5V + 5%
2.5V + 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
VOH
VOL
VIH
VIL
ILI
ILO
Parameter
Test Conditions
Output HIGH Voltage
IOH = –4.0 mA (3.3V)
IOH = –1.0 mA (2.5V)
Output LOW Voltage
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current Vss ≤ VIN ≤ VDD(1)
Output Leakage Current Vss ≤ VOUT ≤ VDDQ,
OE = VIH
3.3V
Min. Max.
2.4 —
— 0.4
2.0 VDD + 0.3
-0.3 0.8
-5 5
-5 5
2.5V
Min. Max.
2.0 —
Unit
V
— 0.4
V
1.7 VDD + 0.3
-0.3 0.7
-5 5
-5 5
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Temp. range
-200
MAX
x18 x36
-166
MAX
x18 x36
Unit
ICC AC Operating
Device Selected,
Com.
Supply Current
OE = VIH, ZZ ≤ VIL,
Ind.
All Inputs ≤ 0.2V or ≥ VDD – 0.2V, typ.(2)
Cycle Time ≥ tKC min.
450 450
475 475
390
400 400 mA
450 450
340
ISB Standby Current Device Deselected,
TTL Input
VDD = Max.,
All Inputs ≤ VIL or ≥ VIH,
ZZ ≤ VIL, f = Max.
Com. 150 150
Ind. 150 150
120 120
120 120
mA
ISBI Standby Current Device Deselected,
Com.
CMOS Input
VDD = Max.,
Ind.
VIN ≤ VSS + 0.2V or ≥VDD – 0.2V
typ.(2)
f=0
110 110
140 140
75
110 110
140 140
75
mA
Note:
1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100µA maximum leakage current when tied to ≤
VSS + 0.2V or ≥ VDD – 0.2V.
2. Typical values are measured at Vcc = 3.3V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc.
Rev. B
03/27/08
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet IS61LPS204818A.PDF ] | |
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| IS61LPS204818A | 1Mb x 36 - 2Mb x 18 36Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM | Integrated Silicon Solution |
| IS61LPS204818A | 1MB x 36/ 2Mb x 18 36Mb SYNCHRONOUS PIPELINED / SINGLE CYCLE DESELECT STATIC RAM | Integrated Silicon Solution |
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