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PDF IS61LPS25672A Data sheet ( Hoja de datos )
| Número de pieza | IS61LPS25672A | |
| Descripción | SINGLE CYCLE DESELECT STATIC RAM | |
| Fabricantes | Integrated Silicon Solution | |
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IS61vPS25672A IS61lPS25672A
IS61vPS51236A IS61lPS51236A
IS61vPS102418A IS61lPS102418A
256K x 72, 512K x 36, 1024K x 18
18Mb SYNCHRONOUS PIPELINED,
Single CYCLE DESELECT STATIC RAM
JUNE 2015
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth ex-
pansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%
VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5%
• JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball
PBGA, and 209-ball (x72) packages
• Lead-free available
DESCRIPTION
The ISSI IS61LPS/VPS51236A, IS61LPS/VPS102418A,
and IS61LPS/VPS25672A are high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and network-
ing applications. The IS61LPS/VPS51236A is organized
as 524,288 words by 36 bits, the IS61LPS/VPS102418A is
organized as 1,048,576 words by 18 bits, and the IS61LPS/
VPS25672A is organized as 262,144 words by 72 bits.
Fabricated with ISSI's advanced CMOS technology, the
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single mono-
lithic circuit. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol Parameter
tkq
Clock Access Time
tkc
Cycle Time
Frequency
250
2.6
4
250
200
3.1
5
200
Units
ns
ns
MHz
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — 1-800-379-4774 1
Rev. P
06/11/2015
1 page  
IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
119 BGA PACKAGE PIN CONFIGURATION-512K x 36 (TOP VIEW)
1 2 3 4 5 67
A VDDQ A
B NC A
A ADSP A
A ADSC A
A VDDQ
A NC
C NC A
A
VDD
A
A NC
D DQc DQPc Vss NC Vss DQPb DQb
E DQc DQc Vss CE Vss DQb DQb
F
VDDQ
DQc
Vss
OE Vss DQb VDDQ
G DQc DQc BWc ADV BWb DQb DQb
H
DQc DQc Vss
GW Vss DQb DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K DQd DQd Vss CLK Vss DQa DQa
L DQd DQd BWd NC BWa DQa DQa
M
VDDQ
DQd
Vss
BWE Vss DQa VDDQ
N DQd DQd Vss A1* Vss DQa DQa
P DQd DQPd Vss A0* Vss DQPa DQa
R NC A MODE VDD NC A NC
T NC NC A A A NC ZZ
U
VDDQ
TMS
TDI
TCK TDO
NC VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
A Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address
Advance
ADSP
Address Status Processor
ADSC
Address Status Controller
GW
Global Write Enable
CLK
Synchronous Clock
CE Synchronous Chip Select
BWx (x=a-d) Synchronous Byte Write Controls
BWE
Byte Write Enable
Symbol
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQd
DQPa-Pd
Vdd
Vddq
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774 5
Rev. P
06/11/2015
5 Page 
IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
TRUTH TABLE(1-8) (3CE option)
OPERATION ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselect Cycle, Power-Down
None H X X L X L X X X L-H High-Z
Deselect Cycle, Power-Down
None L X L L L X X X X L-H High-Z
Deselect Cycle, Power-Down
None L H X L L X X X X L-H High-Z
Deselect Cycle, Power-Down
None L X L L H L X X X L-H High-Z
Deselect Cycle, Power-Down
None L H X L H L X X X L-H High-Z
Snooze Mode, Power-Down
None X X X H X X X X X X
High-Z
Read Cycle, Begin Burst
External L L H L L X X X L L-H
Q
Read Cycle, Begin Burst
External L L H L L X X X H L-H High-Z
Write Cycle, Begin Burst
External L L H L H L X L X L-H
D
Read Cycle, Begin Burst
External L L H L H L X H L L-H
Q
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
External L L H L H L X H H L-H High-Z
Next X X X L H H L H L L-H
Q
Next X X X L H H L H H L-H High-Z
Next H X X L X H L H L L-H
Q
Next H X X L X H L H H L-H High-Z
Next X X X L H H L L X L-H
D
Next H X X L X H L L X L-H
D
Read Cycle, Suspend Burst
Current X X X L H H H H L L-H
Q
Read Cycle, Suspend Burst
Current X X X L H H H H H L-H High-Z
Read Cycle, Suspend Burst
Current H X X L X H H H L L-H
Q
Read Cycle, Suspend Burst
Current H X X L X H H H H L-H High-Z
Write Cycle, Suspend Burst
Current X X X L H H H L X L-H
D
Write Cycle, Suspend Burst
Current H X X L X H H L X L-H
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s
and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are available
on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
Integrated Silicon Solution, Inc. — 1-800-379-4774 11
Rev. P
06/11/2015
11 Page | ||
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| PDF Descargar | [ Datasheet IS61LPS25672A.PDF ] | |
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