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PDF IS61LPD51218A Data sheet ( Hoja de datos )
| Número de pieza | IS61LPD51218A | |
| Descripción | 256K x 36 - 512K x 18 9 Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM | |
| Fabricantes | Integrated Silicon Solution | |
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IS61VPD25636A IS61LPD25636A
IS61VPD51218A IS61LPD51218A
256K x 36, 512K x 18
9 Mb SYNCHRONOUS PIPELINED,
DOUBLE CYCLE DESELECT STATIC RAM
ISSI®
www.DataSheet4U.com
MAY 2005
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Double cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LPD: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPD: VDD 2.5V + 5%, VDDQ 2.5V + 5%
• JEDEC 100-Pin TQFP,
119-pin PBGA and 165-pin PBGA package
DESCRIPTION
The ISSIIS61LPD/VPD25636AandIS61LPD/VPD51218A
are high-speed, low-power synchronous static RAMs de-
signed to provide burstable, high-performance memory for
communication and networking applications. The IS61LPD/
VPD25636A is organized as 262,144 words by 36 bits, and
the IS61LPD/VPD51218A is organized as 524,288 words
by 18 bits. Fabricated with ISSI's advanced CMOS technol-
ogy, the device integrates a 2-bit burst counter, high-speed
SRAM core, and high-drive capability outputs into a single
monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to four
bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
250 200 Units
2.6 3.1
ns
4 5 ns
250 200 MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/09/05
1
1 page  
IS61VPD25636A, IS61VPD51218A, IS61LPD25636A, IS61LPD51218A
ISSI ®
www.DataSheet4U.com
119 BGA PACKAGE PIN CONFIGURATION
512KX18 (TOP VIEW)
1 2 3 4 5 67
A VDDQ
B NC
A
CE2
A ADSP A
A ADSC A
A VDDQ
A NC
C NC
A
A VDD A
A NC
D DQb NC Vss NC Vss DQPa NC
E NC DQb Vss CE Vss NC DQa
F VDDQ
NC
Vss
OE
Vss
DQa
VDDQ
G NC
DQb
BWb
ADV
Vss
NC DQa
H DQb NC Vss GW Vss DQa NC
J VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K NC
DQb Vss CLK Vss
NC DQa
L DQb NC Vss NC BWa DQa NC
M VDDQ DQb Vss BWE Vss
NC VDDQ
N DQb NC Vss A1* Vss DQa NC
P
NC
DQPb
Vss
A0*
Vss
NC DQa
R NC
A
MODE
VDD
NC
A NC
T NC
A
A NC A
A ZZ
U VDDQ
TMS
TDI
TCK TDO
NC VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is
desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2
BWx (x=a,b)
BWE
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write Controls
Byte Write Enable
Symbol
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQb
DQPa-Pb
VDD
VDDQ
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/09/05
5
5 Page 
IS61VPD25636A, IS61VPD51218A, IS61LPD25636A, IS61LPD51218A
ISSI ®
www.DataSheet4U.com
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
TSTG
Storage Temperature
PD Power Dissipation
IOUT Output Current (per I/O)
VIN, VOUT Voltage Relative to Vss for I/O Pins
VIN Voltage Relative to Vss for
for Address and Control Inputs
Value
–55 to +150
1.6
100
–0.5 to VDDQ + 0.5
–0.5 to VDD + 0.5
Unit
°C
W
mA
V
V
VDD Voltage on VDD Supply Relative to Vss
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/09/05
11
11 Page | ||
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| PDF Descargar | [ Datasheet IS61LPD51218A.PDF ] | |
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