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LC8220 の電気的特性と機能

LC8220のメーカーはSanyo Semicon Deviceです、この部品の機能は「JPEG Still Color Image Compression/Decompression LSI」です。


製品の詳細 ( Datasheet PDF )

部品番号 LC8220
部品説明 JPEG Still Color Image Compression/Decompression LSI
メーカ Sanyo Semicon Device
ロゴ Sanyo Semicon Device ロゴ 




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LC8220 Datasheet, LC8220 PDF,ピン配置, 機能
Ordering number : EN*4909A
Preliminaly
CMOS LSI
LC8220
JPEG Still Color Image
Compression/Decompression LSI
Overview
The LC8220 JPEG LSI implements digital still image
compression and decompression conforming to the JPEG
(Joint Photographic Expert Group) standard. The LC8220
includes the baseline system of the ISO 10918 (JPEG)
standard, and requires no external components to construct
an application that performs JPEG compliant
compression/decompression.
Features
• Conforms to the ISO 10918-1 baseline system
• Four quantization tables and four Huffman tables (two
for AC and two for DC) are built in.
• Hardware support for JPEG marker codes
• Built-in bidirectional YUV - RGB converter
• Many color component sampling ratios are supported.
(e.g., YUV 4:1:1 and YMCK 1:1:1:1, etc.)
• Level shift function that can be defined for each
component
• Built-in dual buffers for reduced data transfer load
• Bus sizing function that allows direct connection to 8-,
16-, and 32-bit busses
• Endian control function
• Three independent data buses
Package Dimensions
unit: mm
3153A-QFP160
[LC8220]
SANYO: QFP160
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
32896HA (OT)/D1694TH (OT) No. 4909-1/13

1 Page





LC8220 pdf, ピン配列
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Symbol
VSS
CTLCS
CTLRD
CTLWR
CTLRDY
CTLERR
CTLINT
CPUCTL
CTLSIZE
VDD
VSS
CTLA7
CTLA6
CTLA5
CTLA4
CTLA3
CTLA2
CTLA1
CTLA0
VDD
VSS
CTLD15
CTLD14
CTLD13
CTLD12
CTLD11
CTLD10
CTLD9
CTLD8
VDD
VSS
CTLD7
CTLD6
CTLD5
CTLD4
CTLD3
CTLD2
CTLD1
CTLD0
VDD
VSS
CLK
CLKSEL
RESET
TEST
TESTOUT
MDD10
MDD9
MDD8
VDD
VSS
MDD7
MDD6
MDD5
LC8220
I/O Function
— Ground
I Control bus chip select*2
I Control bus read request*3
I Control bus write request*4
O Control bus ready for read/write requests*5
O Error interrupt request
O Control bus interrupt request
I Connected CPU type setting for the control bus*1
I Bus width selection for the control bus (0: 8 bits, 1: 16 bits)
— +5 V power supply
— Ground
I
I
I
I
Control address bus
I
I
I
I
— +5 V power supply
— Ground
I/O
I/O
I/O
I/O
Control data bus (D15 to D8 are unused if an 8-bit CPU is used.*7)
I/O
I/O
I/O
I/O
— +5 V power supply
— Ground
I/O
I/O
I/O
I/O
Control data bus
I/O
I/O
I/O
I/O
— +5 V power supply
— Ground
I System clock
I Clock divisor selection (0: no divisor, 1: divisor used)*6
I System reset
I Test mode selection (0: normal operation, 1: test mode)*6
O Test result output*8
I/O
I/O Test mode data bus*7
I/O
— +5 V power supply
— Ground
I/O
I/O Test mode data bus*7
I/O
Continued on next page.
No. 4909-3/13


3Pages


LC8220 電子部品, 半導体
LC8220
Specifications
Absolute Maximum Ratings at Ta = 25°C, GND = 0 V
Parameter
Maximum supply voltage
I/O voltages
Operating temperature
Storage temperature
Soldering temperature
Symbol
VDD max
VI, VO
Topr
Tstg
Conditions
Hand soldering: 3 seconds
Reflow soldering: 10 seconds
Ratings
–0.3 to +7.0
–0.3 to VDD + 0.3
–30 to +70
–55 to +125
350
235
Unit
V
V
°C
°C
°C
°C
Allowable Operating Ranges at Ta = –30 to +70°C, GND = 0 V
Parameter
Supply voltage
Input voltage
Symbol
VDD
VIN
Conditions
min typ max Unit
4.5 5.5 V
0
VDD
V
DC Characteristics at Ta = –30 to +70°C, VDD = 4.5 to 5.5 V, GND = 0 V
Parameter
Input high level voltage
Input low level voltage
Input leakage current
Output high level voltage
Output low level voltage
Output leakage current
Oscillator frequency
Current drain
Symbol
VIH
VIL
IL
VOH
VOL
IOZ
fOSC
IDD
Conditions
TTL compatible: CTLCS, CTLRD, CTLWR, CPUCTL,
CTLSIZE, CTLA7 to CTLA0, CLKSEL, RESET, TEST,
CTLD15 to CTLD0
TTL compatible: CPUPX, PXCS, PXRD, PXWR,
PXD31 to PXD0, PXRLS, PXSIZE0
PXSIZE1, CDCS, CDRD, CDWR, CDRLS, CDFLSH,
CPUCD, CDSIZE, CDD15 to CDD0
IOH = –3 mA, TTL compatible: CTLRDY, CTLERR,
CTLINT, TESTOUT, CTLD15 to CTLD0, PXRDY,
PXINT, PXEND, PXD31 to PXD0, CDRDY, CDINT,
CDEND, CDD15 to CDD0
IOH = –3 mA, TTL compatible: CTLRDY, CTLERR,
CTLINT, TESTOUT, CTLD15 to CTLD0, PXRDY,
PXINT, PXEND, PXD31 to PXD0, CDRDY, CDINT,
CDEND, CDD15 to CDD0
For high impedance outputs: CTLD15 to CTLD0,
PXD31 to PXD0, CDD15 to CDD0
CLK
VDD = 5.0 V
min
2.2
–10
VDD – 2.1
–10
typ
145
max
0.8
+10
Unit
V
V
µA
V
0.4 V
+10
16.67
µA
MHz
mA
No. 4909-6/13

6 Page



ページ 合計 : 13 ページ
 
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共有リンク

Link :


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