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IS24C04A の電気的特性と機能

IS24C04AのメーカーはIntegrated Silicon Solutionです、この部品の機能は「1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS24C04A
部品説明 1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS24C04A Datasheet, IS24C04A PDF,ピン配置, 機能
IS24C02A IS24C04A
IS24C08A IS24C16A
®
ISSIwww.DataSheet4U.com
1K-bit/2K-bit/4K-bit/8K-bit/16K-bit
2-WIRE SERIAL CMOS EEPROM
JANUARY 2006
FEATURES
• Two-Wire Serial Interface, I2CTM Compatible
–Bi-directional data transfer protocol
• Wide Voltage Operation
–Vcc = 1.8V to 5.5V
• 400 KHz (2.5V) and 1 MHz (5.0V) Compatible
• Low Power CMOS Technology
–Standby Current less than 6 µA (5.0V)
–Read Current less than 2 mA (5.0V)
–Write Current less than 3 mA (5.0V)
• Hardware Data Protection
–Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
5 ms max @ 2.5V
• Organization:
–IS24C02A, 256x8 (one block of 256 bytes)
–IS24C04A, 512x8 (two blocks of 256 bytes)
–IS24C08A, 1024x8 (four blocks of 256 bytes)
–IS24C16A, 2048x8 (eight blocks of 256 bytes)
• 16 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 100 Years
• Commercial, Industrial and Automotive tempera-
ture ranges
• 8-pin PDIP, 8-pin SOIC, 8-pad DFN, 8-pin
TSSOP, and 8-pin MSOP packages
• Lead-free available
DESCRIPTION
The IS24C02A, IS24C04A, IS24C08A, and
IS24C16A are electrically erasable PROM
devices that use the standard 2-wire interface for
communications. The IS24C02A, IS24C04A,
IS24C08A, and IS24C16A contain a memory array
of 2K-bits (256 x 8), 4K-bits (512 x 8), 8K-bits
(1,024 x 8), and 16K-bits (2,048 x 8), respectively.
Each device is organized into 16 byte pages for
page write mode.
This EEPROM operates in a wide voltage range of
1.8V to 5.5V to be compatible with most application
voltages. ISSI designed this device family to be a
practical, low-power 2-wire EEPROM solution. The
devices are available in 8-pin PDIP, 8-pin SOIC, 8-
pad DFN, 8-pin MSOP, and 8-pin TSSOP pack-
ages.
The IS24C02A/04A/08A/16A maintains compatibil-
ity with the popular 2-wire bus protocol, so it is
easy to use in applications implementing this bus
type. The simple bus consists of the Serial Clock
wire (SCL) and the Serial Data wire (SDA). Using
the bus, a Master device such as a microcontroller
is usually connected to one or more Slave devices
such as this device. The bit stream over the SDA
line includes a series of bytes, which identifies a
particular Slave device, an instruction, an address
within that Slave device, and a series of data, if
appropriate. The IS24C02A/04A/08A/16A has a
Write Protect pin (WP) to allow blocking of any
write instruction transmitted over the bus.
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
01/09/06
1

1 Page





IS24C04A pdf, ピン配列
IS24C02A IS24C04A IS24C08A IS24C16A
ISSI ®
www.DataSheet4U.com
PIN CONFIGURATION
8-Pin DIP, SOIC, DFN, TSSOP, MSOP
PIN CONFIGURATION
8-pad DFN
A0 1
A1 2
A2 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
A0 1
A1 2
A2 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
(Top View)
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses and data
intoandoutofthedevice. TheSDApinisanopendrainoutputand
can be wire-Or'ed with other open drain or open collector
outputs. The SDA bus requires a pullup resistor to Vcc.
A0, A1, A2
The A0, A1 and A2 are the device address inputs. The
IS24C02A uses the A0, A1, and A2 for hardware addressing
and a total of 8 devices may be used on a single bus system.
When the A0, A1, or A2 inputs are left floating, the input
internally defaults to zero.
The IS24C04A uses A1 and A2 pins for hardwire addressing
and a total of four devices may be addressed on a single bus
system. The A0 pin is a no connect in the IS24C04A. When
the A1 or A2 input is left floating, the input internally defaults
to zero.
The IS24C08A only uses the A2 input for hardwire addressing
and a total of two devices may be addressed on a single bus
system. The A0 and A1 pins are no connects in the
IS24C08A. When the A2 input is left floating, the input
internally defaults to zero.
These pins are not used by IS24C16A . The A0, A1, and A2 pins
are no connects in the IS24C16A.
WP
WP is the Write Protect pin. If the WP pin is tied to VCC on
the IS24C02A, IS24C04A, IS24C08A and IS24C016A, the
entire array becomes Write Protected (Read only). When WP
is tied to GND or left floating normal read/write operations are
allowed to the device.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
01/09/06
3


3Pages


IS24C04A 電子部品, 半導体
IS24C02A IS24C04A IS24C08A IS24C16A
ISSI ®
www.DataSheet4U.com
READ OPERATION
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address is
set to “1”. There are three Read operation options: current
address read, random address read and sequential read.
Current Address Read
The IS24C02A/04A/08A/16A contains an internal address
counter which maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation is
either a Read or Write operation addressed to the address
location n, the internal address counter would increment to
address location n+1. When the EEPROM receives the
Slave Addressing Byte with a Read operation (R/W bit set to
“1”), it will respond an ACK and transmit the 8-bit data byte
stored at address location n+1. The Master should not
acknowledge the transfer but should generate a Stop condition
so the IS24C02A/04A/08A/16A discontinues transmission. If
'n' is the last byte of the memory, the data from location '0' will
be transmitted. (Refer to Figure 8. Current Address Read
Diagram.)
Random Address Read
Selective Read operations allow the Master device to
select at random any memory location for a Read
operation. The Master device first performs a 'dummy'
Write operation by sending the Start condition, Slave
address and byte address of the location it wishes to
read. After the IS24C02A/04A/08A/16A acknowledges
the byte address, the Master device resends the Start
condition and the Slave address, this time with the R/W
bit set to one. The EEPROM then responds with its ACK
and sends the data requested. The Master device does
not send an ACK but will generate a Stop condition. (Refer
to Figure 9. Random Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS24C02A/04A/08A/16A sends the initial byte sequence,
the Master device now responds with an ACK indicating
it requires additional data from the IS24C02A/04A/08A/
16A. The EEPROM continues to output data for each
ACK received. The Master device terminates the
sequential Read operation by pulling SDA High (no ACK)
indicating the last data word to be read, followed by a Stop
condition.
The data output is sequential, with the data from address
n followed by the data from address n+1,n+2 ... etc. The
address counter increments by one automatically, allowing
the entire memory contents to be serially read during
sequential Read operation. When the memory address
boundary of 255, 511, 1023, or 2047 (depending on the
device) is reached, the address counter “rolls over” to
address 0, and the device continues to output data.
(Refer to Figure 10. Sequential Read Diagram).
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
01/09/06

6 Page



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共有リンク

Link :


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IS24C04-3

2-WIRE SERIAL CMOS EEPROM

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ISSI
IS24C04A

1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM

Integrated Silicon Solution
Integrated Silicon Solution


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