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PDF ADP120 Data sheet ( Hoja de datos )
| Número de pieza | ADP120 | |
| Descripción | 100mA Low Quiescent Current CMOS Linear Regulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Input voltage range: 2.3 V to 5.5 V
Output voltage range: 1.2 V to 3.3 V
Output current: 100 mA
Low quiescent current
IGND = 11 μA with zero load
IGND = 22 μA with 100 mA load
Low shutdown current: <1 μA
Low dropout voltage
60 mV @ 100 mA load
High PSRR
73 dB @ 1 kHz at VOUT = 1.2 V
70 dB @ 10 kHz at VOUT = 1.2 V
Low noise: 40 μV rms at VOUT = 1.2 V
No noise bypass capacitor required
Initial accuracy: ±1%
Stable with small 1 μF ceramic output capacitor
16 fixed output voltage options
Current-limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
4-ball 0.4 mm pitch WLCSP
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post regulation
GENERAL DESCRIPTION
The ADP120 is a low quiescent current, low dropout, linear
regulator that operates from 2.3 V to 5.5 V and provides up to
100 mA of output current. The low 60 mV dropout voltage at
100 mA load improves efficiency and allows operation over a
wide input voltage range. The low 25 μA of quiescent current at
full load makes the ADP120 ideal for battery-operated portable
equipment.
100 mA, Low Quiescent Current,www.DataSheet4U.com
CMOS Linear Regulator
ADP120
TYPICAL APPLICATIONS CIRCUITS
VIN = 2.3V
+
1µF
1 VIN
2 GND
VOUT 5
VOUT = 1.8V
+
1µF
3 EN
NC 4
NC = NO CONNECT
Figure 1. ADP120 TSOT with Fixed Output Voltage, 1.8 V
VIN = 2.3V
+
1µF
VIN
VOUT
VOUT = 1.8V
+
1µF
EN GND
Figure 2. ADP120 WLCSP with Fixed Output Voltage, 1.8 V
The ADP120 is available in 16 fixed output voltage options,
ranging from 1.2 V to 3.3 V. The part is optimized for stable
operation with small 1 μF ceramic output capacitors. The
ADP120 delivers good transient performance with minimal
board area.
Short-circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP120 is available
in a tiny 5-lead TSOT and a 4-ball 0.4 mm pitch WLCSP for the
smallest footprint solution for use in a variety of portable
applications.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND Pins
VOUT to GND Pins
EN to GND Pins
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6 V
−0.3 V to VIN
−0.3 V to +6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP120 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (TJ) of
the device is dependent on the ambient temperature (TA), the
power dissipation of the device (PD), and the junction-to-ambient
thermal resistance of the package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
ADP120www.DataSheet4U.com
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The speci-
fied values of θJA are based on a four-layer, 4 in. × 3 in. PCB.
Refer to JESD 51-7 and JESD 51-9 for detailed information
regarding board construction. For additional information, see
Application Note AN-617, MicroCSPTM Wafer Level Chip Scale
Package.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a four-layer board. JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as
thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make ΨJB more useful in real-world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD)
using the formula
TJ = TB + (PD × ΨJB)
Refer to JESD51-8, JESD51-9, and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
4-Ball, 0.4 mm Pitch WLCSP
θJA ΨJB Unit
170 43 °C/W
260 58 °C/W
ESD CAUTION
Rev. A | Page 5 of 20
5 Page 
THEORY OF OPERATION
The ADP120 is a low quiescent current, low dropout linear
regulator that operates from 2.3 V to 5.5 V and provides up
to 100 mA of output current. Drawing a low 22 μA of quies-
cent current (typical) at full load makes the ADP120 ideal
for battery-operated portable equipment. Shutdown current
consumption is typically 100 nA.
Optimized for use with small 1 μF ceramic capacitors, the
ADP120 provides excellent transient performance.
VIN
GND
SHORT CIRCUIT,
UVLO, AND
THERMAL
PROTECT
VOUT
R1
EN
SHUTDOWN
0.8V REFERENCE
R2
Figure 27. Internal Block Diagram
ADP120www.DataSheet4U.com
Internally, the ADP120 consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is controlled
by the error amplifier. The error amplifier compares the reference
voltage with the feedback voltage from the output and amplifies
the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate of
the PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.
The ADP120 is available in 16 output voltage options, ranging
from 1.2 V to 3.3 V. The ADP120 uses the EN pin to enable and
disable the VOUT pin under normal operating conditions. When
EN is high, VOUT turns on; when EN is low, VOUT turns off.
For automatic startup, EN can be tied to VIN.
Rev. A | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADP120.PDF ] | |
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