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PDF LC78624E Data sheet ( Hoja de datos )
| Número de pieza | LC78624E | |
| Descripción | Compact Disc Player DSP | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : EN5811
CMOS LSI
LC78624E
Compact Disc Player DSP
Overview
The LC78624E is a CMOS LSI that implements the signal
processing and servo control required by compact disc
players. Including an EFM-PLL and text decoder, the
LC78624E strictly limits functionality to basic signal
processing and servo system operation to achieve the best
cost-performance balance for low-end players. As basic
functions, the LC78624E provides demodulation of the
EFM signal from the optical pickup, de-interleaving, error
detection and correction, and processes servo commands
sent from the control microcontroller.
Functions
• Input signal processing: The LC78624E takes an HF
signal as input, digitizes (slices) that signal at a precise
level, converts that signal to an EFM signal, and
generates a PLL clock with an average frequency of
4.3218 MHz by comparing the phases of that signal and
an internal VCO.
• Precise reference clock and necessary internal timing
generation using an external 16.9344 MHz crystal
oscillator
• Disk motor speed control using a frame phase difference
signal generated from the playback clock and the
reference clock
• Frame synchronization signal detection, protection and
interpolation to assure stable data readout
• EFM signal demodulation and conversion to 8-bit
symbol data
• Subcode data separation from the EFM demodulated
signal and output of that data to an external
microcontroller
• Subcode Q signal output to a microcontroller over the
serial I/O interface after performing a CRC error check
(LSB first)
• Serial output to a microcontroller via the text decoder of
the song titles and other text data stored in the Subcode
R through W channels of the read-in area
• Demodulated EFM signal buffering in internal RAM to
handle up to ±4 frames of disk rotational jitter
• Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
• Error detection, correction, and flag processing (error
correction scheme: dual C1 plus dual C2 correction)
• The LC78624E sets the C2 flags based on the C1 flags
and a C2 check, and then performs signal interpolation
or muting depending on the C2 flags. The interpolation
circuit uses a dual-interpolation scheme. The previous
value is held if the C2 flags indicate errors two or more
times consecutively.
• Support for command input from a microcontroller:
commands include track jump, focus start, disk motor
start/stop, muting on/off and track count (8 bit serial
input)
• Built-in digital output circuits.
• Arbitrary track counting to support high-speed data
access
• Zero cross muting
• Supports the implementation of a double-speed dubbing
function.
• Support for bilingual applications.
• General-purpose I/O ports: 5 pins
Features
• 64 pin QFP
• 5 V single-voltage power supply
Package Dimensions
unit: mm
3159-QFP64E
[LC78624E]
SANYO: QIP64E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
20698RM (OT) No. 5811-1/27
1 page  
LC78624E
Figure 1 Command Input
A09894
Figure 2 Subcode Q Output
A09895
Figure 3 Subcode Output
A09896
No. 5811-5/27
5 Page 
LC78624E
• CLV mode
In CLV mode the LC78624E detects the disk speed from the HF signal and provides proper linear speed using
several different control schemes by switching the DSP internal modes. The PWM reference period corresponds to
a frequency of 7.35 kHz. The V/P pin outputs a high level during rough servo and a low level during phase control.
Internal mode
Rough servo (velocity too low)
Rough servo (velocity too high)
Phase control (PCK locked)
CLV+
High
Low
PWM
CLV–
Low
High
PWM
V/P
High
High
Low
• Rough servo gain switching
Code
$A8
$A9
Command
DISC 8 cm SET
DISC 12 cm SET
RES = low
q
For 8 cm disks, the rough servo mode CLV control gain can be set about 8.5 dB lower than the gain used for 12 cm
disks.
• Phase control gain switching
Code
$B1
$B2
$B3
$B0
Command
CLV PHASE COMPARATOR DIVISOR: 1/2
CLV PHASE COMPARATOR DIVISOR: 1/4
CLV PHASE COMPARATOR DIVISOR: 1/8
NO CLV PHASE COMPARATOR DIVISOR USED
RES = low
q
The phase control gain can be changed by changing the divisor used by the dividers in the stage immediately
preceding the phase comparator.
A09906
No. 5811-11/27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet LC78624E.PDF ] | |
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